74AC11074 Datasheet, PDF (4/6 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A – DECEMBER 1986 – REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range,
V_CC = 3.3 V ± 0.3 V (see Figure 1)
TA = 25°C
MIN MAX
MIN MAX UNIT
fclock Clock frequency
tw
Pulse duration
PRE or CLR low
CLK low or high
0 100
4
5
0 100 MHz
4
ns
5
tsu
Setup time before CLK↑
Data high or low
5
PRE or CLR inactive
1
5
ns
1
th
Hold time after CLK↑
0
0
ns
timing requirements over recommended operating free-air temperature range,
V_CC = 5 V ± 0.5 V (see Figure 1)
TA = 25°C
MIN
MIN MAX
fclock Clock frequency
tw
Pulse duration
PRE or CLR low
CLK low or CLK high
0 125
0
4
4
4
4
tsu
Setup time before CLK↑
Data high or low
3.5
3.5
PRE or CLR inactive
1
1
th
Hold time after CLK↑
0
0
MAX
125
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN TYP MAX
MIN MAX UNIT
fmax
tPLH
tPHL
tPLH
tPHL
PRE or CLR
CLK
Q or Q
Q or Q
100 125
100
MHz
1.5 5.8 9.3 1.5
10
ns
1.5 6.5 11.4 1.5 12.2
1.5 7.7 10.5 1.5 11.3
ns
1.5 7.3 9.7 1.5 10.6
switching characteristics over recommended operating free-air temperature range,
V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN TYP MAX
MIN MAX UNIT
fmax
tPLH
tPHL
tPLH
tPHL
PRE or CLR
CLK
Q or Q
Q or Q
125 150
1.5 4.2
1.5 4.7
1.5 5.4
1.5
5
125
6.6 1.5
8.2 1.5
7.5 1.5
6.9 1.5
MHz
7.1
ns
9
8.2
ns
7.5
operating characteristics, V_CC = 5 V, T_A = 25°C
PARAMETER
Cpd Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP UNIT
30 pF
4
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