TVP3026 Datasheet, PDF (39/107 Pages) Texas Instruments – Video Interface Palette

Table 2–17. Multiplex Mode and Bus-Width Selection (Continued)
MODE
SUB-
MODE
TRUE-
COLOR-
CONTROL
REGISTER
(INDEX
0x18)
MULTIPLEX-
CONTROL
REGISTER
(INDEX
0x19)
DATA
BITS
PER
PIXEL
(see
Note 3)
PIXEL
BUS
WIDTH
MULTI-
PLEX
RATIO
(see
Note 4)
OVERLAY
BITS
PER
PIXEL
TABLE
REFERENCE
(see
Note 5)
5
0x05
0x52
16
16
1
NA
d13
16-bit XGA
R-G-B
0x05
0x53
16
32
2
NA
d14
5– 6 – 5
0x05
0x54
16
64
4
NA
d15
6
0x04
0x52
15
16
1
1
d16
16-bit
TARGA
0x04
0x53
15
32
2
1
d17
O-R-G-B
Direct- _{1–5– 5– 5}
0x04
0x54
15
64
4
1
d18
Color
7
0x03
0x52
16
16
1
NA
d19
16-bit
R-G-B
0x03
0x53
16
32
2
NA
d20
6–6–4
0x03
0x54
16
64
4
NA
d21
8
0x01
0x52
12
16
1
4
d22
16-bit
R-G-B-O
0x01
0x53
12
32
2
4
d23
4–4–4–4
0x01
0x54
12
64
4
4
d24
0x56
0x5B
24
32
4:3
NA
d1
1
Packed-24
0x56
0x5C
24
64
8:3
NA
d2
R-G-B
0x5E
0x5B
24
32
5:4
NA
d3
8–8–8
0x5E
0x5C
24
64
5:2
NA
d4
0x57
0x5B
24
32
4:3
NA
d5
2
Packed-24
0x57
0x5C
24
64
8:3
NA
d6
True-
Color
B-G-R
8–8–8
0x5F
0x5F
0x5B
0x5C
24
32
5:4
24
64
5:2
NA
NA
d7
d8
3
0x46
0x5B
24
32
1
NA
d9
32-Bit
X-R-G-B
0x46
0x5C
24
64
2
NA
d10
4
0x47
0x5B
24
32
1
NA
d11
32-bit
B-G-R-X
0x47
0x5C
24
64
2
NA
d12
NOTES: 3. Data bits per pixel is the number of bits of pixel information used as color data for each displayed pixel, often
referred to as the number of bit planes.
4. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 64-bit pixel bus width and 8 bit planes, each bus load is
comprised of 8 pixels. The RCLK frequency must be chosen as a function of the multiplex mode selected.
The RCLK frequency is not automatically set by mode selection; it must be set by programming the loop
clock PLL registers.
5. This column is a reference to Tables 2–18 through 2–21, where the actual manipulation of pixel information
and pixel latching sequences are illustrated for each of the multiplexing modes. For the pseudo-color pixel
latching sequence (V1 and S1 through S12) refer to Table 2–18. For the packed-24 mode pixel latching
sequence associated with the direct-color and true-color modes, refer to Table 2–19. For the direct-color
mode pixel latching sequence, refer to Table 2–20 for little-endian format and to Table 2–21 for big-endian
format.
2–25