TVP3026 Datasheet, PDF (103/107 Pages) Texas Instruments – Video Interface Palette

Appendix F
Changes Made For TVP3026 Revision B
Functional Changes
• Process Change / Die Shrink – The process was changed from 0.8 micron CMOS to 0.72 micron
CMOS.
• PLL Loop Filter and Charge Pump – The loop filter parameters and charge pump were modified
to further enhance the stability of the PLL.
• Crystal Oscillator Circuit – The crystal oscillator circuit was changed to a dc coupled input. This
causes the circuit to oscillate at the crystal frequency as opposed to the slight difference seen
in the A revision due to its ac coupled input.
• ESD Structures – The ESD structures were slightly modified to accommodate for changes in
process parameters and feature sizes.
• Internal Timing Change – An internal timing change was made to improve pixel port latch timing
for the 1:1 multiplex modes.
Programming Changes
• PLL N-Value Registers – Bits 7 and 6 of the PLL N-value register for all PLLs are do not cares.
It is not necessary to program these bits to 11.
• Loop Clock PLL M-Value Register Programming – Loop clock PLL M-value register programming
is changed as shown in Table 2–15. For the 4:3 multiplex mode, the silicon revision register
(index: 0x01) must be tested to determine the value for the M-value register.
• Latch Control Register Programming – Latch control register (index: 0x0F) programming is
changed as shown in Table 2-16. For the 4:3 multiplex mode, the silicon revision register (index:
0x01) must be tested to determine the value for the latch control register.
• Silicon Revision Register – The silicon revision register (index: 0x01) indicates revision A when
≤ 0x20 and indicates revision B when ≥ 0x21.
F–1