TMS320C6713B_10 Datasheet, PDF (38/154 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
DEVICE CONFIGURATIONS (CONTINUED)
Table 23. C6713B Device Multiplexed/Shared Pins
NAME
MULTIPLEXED PINS
PYP
GDP/
ZDP
DEFAULT
FUNCTION
CLKOUT2/GP[2]
82 Y12 CLKOUT2
DEFAULT SETTING
DESCRIPTION
GP2EN = 0
(GPEN register bit)
GP[2] function disabled,
CLKOUT2 enabled
When the CLKOUT2 pin is enabled,
the CLK2EN bit in the EMIF global
control register (GBLCTL) controls the
CLKOUT2 pin.
CLK2EN = 0: CLKOUT2 held high
CLK2EN = 1: CLKOUT2 enabled
to clock [default]
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1
CLKS0/AHCLKR0
DR0/AXR0[0]
DX0/AXR0[1]
FSR0/AFSR0
FSX0/AFSX0
CLKR0/ACLKR0
CLKX0/ACLKX0
CLKS1/SCL1
DR1/SDA1
DX1/AXR0[5]
FSR1/AXR0[7]
CLKR1/AXR0[6]
CLKX1/AMUTE0
To use these software-configurable
GPIO pins, the GPxEN bits in the GP
Enable Register and the GPxDIR bits
in the GP Direction Register must be
properly configured.
GPxEN = 1: GP[x] pin enabled
No Function
GPxDIR = 0: GP[x] pin is an input
GPxDIR = 0 (input)
GPxDIR = 1: GP[x] pin is an
6
1
C1 GP[5](EXT_INT5)
C2 GP[4](EXT_INT4)
GP5EN = 0 (disabled)
GP4EN = 0 (disabled)
[(GPEN register bits)
output
To use AMUTEIN0/1 pin function, the
GP[x] function disabled] _{GP[5]/GP[4] pins must be configured}
as an input, the INEN bit set to 1, and
the polarity through the INPOL bit
selected in the associated McASP
AMUTE register.
28 K3
27 J1
By default, McBSP0 peripheral pins are
enabled upon reset (McASP0 pins are
20 H2
MCBSP0DIS = 0
disabled).
24
J3
McBSP0 pin function
(DEVCFG register bit)
McASP0 pins disabled,
To enable the McASP0 peripheral pins,
21 H1
McBSP0 pins enabled the MCBSP0DIS bit in the DEVCFG
19 H3
16 G3
register must be set to 1 (disabling the
McBSP0 peripheral pins).
8 E1
By default, McBSP1 peripheral pins are
37 M2
32 L2
MCBSP1DIS = 0
(DEVCFG register bit)
enabled upon reset (I2C1 and McASP0
pins are disabled).
38
36
McBSP1 pin function I2C1 and McASP0 pins
M3
disabled, McBSP1 pins
M1
enabled
To enable the I2C1 and McASP0
peripheral pins, the MCBSP1DIS bit in
the DEVCFG register must be set to 1
33 L3
(disabling the McBSP1 peripheral pins).
38
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