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TLC32046C Datasheet, PDF (37/57 Pages) Texas Instruments – Wide-Band Analog Interface Circuit | |||
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3.5.3 Serial Port â AIC Output Signals, CL = 30 pF for SHIFT CLK Output, CL = 15 pF
For All Other Outputs, TLC32046C and TLC32046I
PARAMETER
MIN TYPâ MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
380
45%
ns
3
8 ns
3
8 ns
55%
td(CH-FL) Delay from SCLKâ to FSR/FSX/FSDâ
td(CH-FH) Delay from SCLKâ to FSR/FSX/FSDâ
td(CH-DR) DR valid after SCLKâ
td(CH-EL) Delay from SCLKâ to EODX/EODRâ in word mode
td(CH-EH) Delay from SCLKâ to EODX/EODRâ in word mode
tf(EODX) EODX fall time
tf(EODR) EODR fall time
td(CH-EL) Delay from SCLKâ to EODX/EODRâ in byte mode
td(CH-EH) Delay from SCLKâ to EODX/EODRâ in byte mode
td(MH-SL) Delay from MSTR CLKâ to SCLKâ
td(MH-SH) Delay from MSTR CLKâ to SCLKâ
â Typical values are at TA = 25°C.
30
ns
35
90 ns
90 ns
90 ns
90 ns
2
8 ns
2
8 ns
90 ns
90 ns
65 170 ns
65 170 ns
3.5.4 Serial Port â AIC Output Signals, CL = 30 pF for SHIFT CLK Output, CL = 15 pF
For All Other Outputs, TLC32046M
PARAMETER
MIN TYPâ MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
400
45%
ns
3
ns
3
ns
55%
td(CH-FL) Delay from SCLKâ to FSR/FSX/FSDâ
td(CH-FH) Delay from SCLKâ to FSR/FSX/FSDâ
td(CH-DR) DR valid after SCLKâ
td(CH-EL) Delay from SCLKâ to EODX/EODRâ in word mode
td(CH-EH) Delay from SCLKâ to EODX/EODRâ in word mode
tf(EODX) EODX fall time
tf(EODR) EODR fall time
td(CH-EL) Delay from SCLKâ to EODX/EODRâ in byte mode
td(CH-EH) Delay from SCLKâ to EODX/EODRâ in byte mode
td(MH-SL) Delay from MSTR CLKâ to SCLKâ
td(MH-SH) Delay from MSTR CLKâ to SCLKâ
â Typical values are at TA = 25°C.
30 250 ns
35 250 ns
250 ns
250 ns
250 ns
2
ns
2
ns
250 ns
250 ns
65 170 ns
65 170 ns
3â7
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