DAC5686 Datasheet, PDF (36/46 Pages) Texas Instruments – 16-BIT, 500-MSPS, 2X16X INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER

DAC5686
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
www.ti.com
MSB
dualclk
0
DDS_gain[1:0]
0
0
Register Name: config_usb
rspect
0
qflag
0
pll_rng[1:0]
0
0
LSB
rev_bbus
0
dualclk: When asserted, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock and
CLK2/CLK2C is the DAC output clock. These two clocks must be phase-aligned within ±500 ps to function
properly. When deasserted, CLK2/CLK2C is the DAC output clock and is divided down to generate the input data
clock, which is output on PLLLOCK. Dual clock mode is only available when PLLVDD = 0.
DDS_gain[1:0]: Controls the gain of the DDS so that the overall gain of the DDS is unity. It is important to
ensure that max(abs(cos(ωt) + sin(ωt))) < 1. At different frequencies, the summation produces different maximum
outputs and must be reduced. The simplest is fs/4 mode where the maximum is 1 and the gain multiply should
be 1 to maintain unity. However, due to the fact that the digital logic does a divide-by-two in this summation, the
gain necessary to achieve unity must be double (DDS_gain[1:0] = 01). Table 9 shows the digital gain necessary
and the actual signal gain needed to make the above equation have a maximum value of 1.
DDS_gain [1:0]
00
01
10
11
Table 9. Digital Gain for DDS
DIGITAL GAIN
1.40625
2
1.59375
1.40625
SIGNAL GAIN FOR UNITY
0.703125
1
0.7936
0.703125
rspect: When asserted, the sin term is negated before being used in mixing. This gives the reverse spectrum in
single-sideband mode.
qflag: When asserted, the QFLAG pin is used during interleaved data input mode to identify the Q sample. When
deasserted, the TXENABLE pin transition is used to start an internal toggling signal, which is used to interpret
the interleaved data sequence; the first sample clocked into the DAC5686 after TXENABLE goes high is routed
through the A data path.
PLL_rng[1:0]: Increases the PLL VCO VtoI current, summarized in Table 10. See Figure 17 for the effect on
VCO gain and range.
Table 10. PLL VCO Vtol Current Increase
PLL_rng[1:0]
00
01
10
11
VtoI CURRENT INCREASE
nominal
15%
30%
45%
rev_bbus[1:0]: When asserted, pin 92 changes from DB15 to DB0, pin 91 changes from DB14 to DB1, etc.,
reversing the order of the DB[15:0] pins.
Register Name: daca_offset_lsb (2s complement)
MSB
LSB
daca_offset[7:0]
0
0
0
0
0
0
0
0
36