DAC3283 Datasheet, PDF (36/50 Pages) Texas Instruments – Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)

DAC3283
SLAS693A – MARCH 2010 – REVISED APRIL 2010
www.ti.com
13
16
A Data In
16
S
qma_offset
{-4096, -4095, … , 4095}
A Data Out
16
B Data In
16
S
B Data Out
13
qmb_offset
{-4096, -4095, … , 4095}
Figure 43. Digital Offset Block Diagram
TEMPERATURE SENSOR
The DAC3283 incorporates a temperature sensor block which monitors the temperature by measuring the
voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation
(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement
value representing the temperature in degrees Celsius.
The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled
(tsense_ena = 1 in register CONFIG24) a conversion takes place each time the serial port is written or read. The
data is only read and sent out by the digital block when the temperature sensor is read in register CONFIG5. The
conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on
the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other
clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is
enabled even when the device is in sleep mode.
In order for the process described above to operate properly, the serial port read from CONFIG5 must be done
with an SCLK period of at least 1µs. If this is not satisfied the temperature sensor accuracy is greatly reduced.
POWER-UP SEQUENCE
The following startup sequence is recommended to power-up the DAC3283:
• Set TXENABLE low.
• Supply 1.8V to DACVDD18, DIGVDD18, CLKVDD18 and VFUSE simultaneously and 3.3V to AVDD33.
Within AVDD33 the multiple AVDD33 pins should be powered up simultaneously. The 1.8V and 3.3V supplies
can be powered up simultaneously or in any order.
There are no specific requirements on the ramp rate for the supplies.
• Provide all LVPECL inputs: DACCLKP/N and if used OSTRP/N.
• Program the SIF registers.
• Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N and FRAMEP/N) simultaneously.
• Sync the clock dividers and FIFO. After a FRAMEP/N low-to-high transition, clock divider syncing must be
disabled by setting clkdiv_sync_ena (CONFIG18, bit 1) to 0. Optionally, disable FIFO syncing by setting
fifo_reset_ena (CONFIG0, bit 5) and multi_sync_ena (CONFIG0, bit 4) to 0. Except when in Multi-DAC
operation it is recommended to sync the DACs and their FIFO’s only once during initialization.
• Enable transmit of data by asserting the TXENABLE pin.
SLEEP MODES
The DAC3283 features independent sleep control of each DAC (sleepa and sleepb), their corresponding clock
path (clkpath_sleep_a and clkpath_sleep_b) as well as the clock input receiver of the device (clkrecv_sleep). The
sleep control of each of these components is done through the SIF interface and is enabled by setting a 1 to the
corresponding sleep register.
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