TMS320F2809_08 Datasheet, PDF (35/140 Pages) Texas Instruments – Digital Signal Processors

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M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Peripheral Frame 2
L0 & L1 SARAMs
OTP
Flash
H0 SARAM
Boot-ROM
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007
Table 3-6. Wait-states
WAIT-STATES COMMENTS
0-wait
Fixed
0-wait
Fixed
0-wait (writes) Fixed. The eCAN peripheral can extend a cycle as needed.
2-wait (reads) Back-to-back writes will introduce a 1-cycle delay.
0-wait (writes)
2-wait (reads)
Fixed
0-wait
Programmable,
1-wait minimum
Programmed via the Flash registers. 1-wait-state operation
is possible at a reduced CPU frequency. See Section 3.2.5
for more information.
Programmable,
0-wait minimum
Programmed via the Flash registers. 0-wait-state operation
is possible at reduced CPU frequency. The CSM password
locations are hardwired for 16 wait-states. See
Section 3.2.5 for more information.
0-wait
Fixed
1-wait
Fixed
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Functional Overview
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