PCI2040PGE Datasheet, PDF (35/78 Pages) Texas Instruments – PCI2040 PCI-DSP Bridge Controller

4.3 PCI Command Register
The system software accesses the status and command registers for error recovery, diagnostic, and control. This
register is provided to enable coarse control over a device’s ability to generate and respond to PCI cycles.
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
PCI command
Type
R
R
R
R
R
R
R RW R RW R
R
R
R RW RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
15−10
9
8
7
6
5
4
3
2
1
0
Register:
Type:
Offset:
Default:
PCI command
Read-only, Read/Write
04h
0000h
FIELD NAME
RSVD
FBB−EN
SERR_EN
STEP_EN
PERR_EN
VGA_EN
MWI_EN
Special
MAST_EN
MEM_EN
IO_EN
TYPE
R
R
RW
R
RW
R
R
R
R
RW
RW
Table 4−3. PCI Command Register
DESCRIPTION
Reserved. Bits 15−10 return 0s when read.
Fast back-to-back (FBB) enable. This bit controls whether or not the device is allowed to perform
back-to-back capability for bus master transaction. This bit is hardwired to 0 and indicates that FBB
transfers are not supported by PCI2040.
System error (SERR) enable. This bit is an enable for the output driver on the SERR pin. If this bit is
cleared and a system error condition is set inside PCI2040, then the error signal will not appear on the
external SERR pin.
Address/data stepping control. This bit indicates whether or not the device performs address stepping.
Since the PCI2040 does not require address stepping, this bit is hardwired to 0.
Parity error response enable. This bit controls whether or not the device responds to detected parity
errors. If this bit is set, then the PCI2040 responds normally to parity errors. If this bit is cleared, then
the PCI2040 ignores detected parity errors.
VGA palette snoop. This bit is not applicable for PCI2040 and is hardwired to a 0.
Memory write and invalidate enable. This bit enables the device to use the memory write and invalidate
command. Since the PCI2040 does not support MWI but uses MW instead, this bit is hardwired to 0.
Special cycle. This bit controls the device’s response to special cycle commands. Since PCI2040 does
not monitor any special commands, this bit is set to 0.
Bus master control. This bit allows a PCI device to function as a bus master. This bit is always 0 indicating
PCI2040 does not support PCI mastering.
Memory space enable. This bit enables the device to respond to memory accesses to any of the defined
base address memory regions. If this bit is cleared, then the PCI2040 will not respond to
memory-mapped accesses.
I/O space control. This bit enables the device to respond to I/O accesses within its defined base address
register I/O regions.
4−3