PCI2040PGE Datasheet, PDF (31/78 Pages) Texas Instruments – PCI2040 PCI-DSP Bridge Controller

3.11 Example Transactions on the General-Purpose Bus
This section describes some example transactions on the GP bus.
3.11.1 General-Purpose Bus Word Write
The first diagram, Figure 3−4, depicts a word (16−bits) write to a device residing on the GP bus. The event flow is
as follows:
1. All signals are in a deasserted state except for GP_RDY. The PCI2040 is driving the address and data bus
to a stable but unknown value.
2. The GP_CS is driven low. The data bus (GPD15−GPD0) is driven with the data the PCI2040 obtained from
the PCI bus. In this case, the data is BBAAh. The address bus (GPA5−GPA0) is driven with the address
the PCI2040 obtained from the PCI bus. For example, if the address on the PCI bus is FF0B0h, then this
address would translate to a GP bus address of 2Ch.
3. The GP_WR strobe is driven low indicating a write to the device on the GP bus.
4. The GP_WR strobe is driven high. Typically, a device on the GP bus latches the data on the rising edge
of the GP_WR strobe. But as the figure shows, the data is valid on both the falling edge and the rising edge
of the write strobe. The PCI2040 samples the GP_RDY signal before it deasserts the GP_WR strobe. In
this case, the GP_RDY signal is low indicating to the PCI2040 that the device is ready for data.
5. The transaction completes by deasserting the GP_CS.
1
2
PCI_CLK
GP_RST
GP_CS
GPD[15:0]
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _GPA[5:0]
ÎÎÎÎÎÎÎ _{GP_WR}
GP_RD
GP_RDY
3
4
5
BBAA
2C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 3−4. General-Purpose Bus Word Write
3.11.2 General-Purpose Bus Word Read
The second diagram, Figure 3−5, shows a word read from a device on the GP bus. The event flow is as follows:
1. All signals are in a deasserted state except for GP_RDY. The PCI2040 is driving the address and data bus
to a stable but unknown value.
2. The GP_CS is driven low. The data bus (GPD15−GPD0) is placed in a high impedance state. The address
bus is driven with the address the PCI2040 obtained from the PCI bus.
3. The GP_RD strobe is driven low indicating a read to the device on the GP bus. Sometime later during
clock 3, the device on the GP bus drives valid data on the data bus.
4. The GP_RD strobe is driven high. The PCI2040 samples the GP_RDY before it deasserts GP_RD. If
GP_RDY is sampled asserted, then the PCI2040 deasserts GP_RD strobe and latches the data on the GP
bus. If GP_RDY is sampled deasserted, then the PCI2040 keeps GP_RD asserted and waits for the
GP_RDY strobe to be asserted before it deasserts the GP_RD strobe.
3−11