ADS7871 Datasheet, PDF (35/42 Pages) Texas Instruments – 14-BIT, 48-KSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE

ADS7871
www.ti.com
SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
Mode 1
In this mode, the serial interface configures itself to clockout a conversion result as soon as a conversion is
started. This is useful since a read instruction is not required so eight SCLK cycles are saved. This mode
operates like an implied sixteen bit read instruction byte for ADDR = 1 was sent to the ADS7871 after starting
the conversion.
It is not necessary to wait for the end of the conversion to start clocking out conversion results. The last
completed conversion at the sampling edge of SCLK is read back (whether a conversion is in progress or not).
Mode 2
This mode is similar to Mode 1 except that the conversion result is provided LS byte first (equivalent to a sixteen
bit read from ADDR = 0).
Figure 41 and Figure 42 show timing examples of an automatic read back operation using mode 2. In Figure 41,
the result of the previous conversion is retrieved. This example is for LSB first, CCLK divider = 2, and SCLK
active on the rising edge. The data may be read back immediately after the start conversion instruction. It is
not necessary to wait for the conversion to actually start (or finish).
First output bit loaded in the output register
The remaining output bits loaded in the output register
SCLK
DIN
DOUT
ÓÓÓÓÓÓÓ_{M0 ÓÓM1 ÓÓM2ÓÓM3ÓÓGÓÓ0 GÓÓ1 ÓÓG2 ÓÓ1} ÓÓÓÓÓ_OVRÓÓÓ₀ÓÓÓ_BÓÓÓ_{0 B}ÓÓÓ₁ ÓÓÓ_B2 ÓÓÓ_B3 ÓÓÓ_B4ÓÓÓ_B5ÓÓÓ_BÓÓÓ_{6 B}ÓÓÓ₇ ÓÓÓ_B8 ÓÓÓ_B9 ÓÓÓ_B10ÓÓÓ_B11ÓÓÓ_B1ÓÓÓ_{2 B}ÓÓÓ₁₃ ÓÓÓ
CS
CCLK
BUSY
Figure 41. Timing Diagram for Automatic Read Back of Previous Conversion Result Using Mode 2
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