ADS7871 Datasheet, PDF (28/42 Pages) Texas Instruments – 14-BIT, 48-KSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE

ADS7871
SLAS370C − APRIL 2002 − REVISED OCTOBER 2004
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Reference/Oscillator Configuration Register
The Reference/Oscillator Configuration register (ADDR = 7) determines whether the internal oscillator is used
(OSCE and OSCR), whether the internal voltage reference and buffer are on or off (REFE and BUFE), and whether
the reference is 2.5 V, 2.048 V, or 1.15 V as shown in Figure 31.
REFERENCE/OSCILLATOR REGISTER
ADDR
D7 (MSB)
D6
7
0
0
D5
D4
D3
D2
D1
OSCR
OSCE
REFE
BUFE
R2V
ADDR = 7
BIT SYMBOL
D7−D6
—
D5
OSCR
NAME
—
Oscillator Control
VALUE
0
0
1
FUNCTION
These bits are reserved and must always be set to 0.
Source of clock for internal VREF is CCLK pin.
Clocking signal comes from the internal oscillator.
D4
OSCE
Oscillator Enable
0
CCLK is configured as an input.
1
CCLK outputs a 2.5-MHz signal (70 µA).
D3
REFE
Reference Enable
D2
BUFE
Buffer Enable
0
Reference is powered down.
1
Reference is powered up.
0
Buffer is powered down and draws no current.
1
Buffer is powered up and draws 150 µA of current.
D1
R2V
2-V Reference
D0
RBG
Bandgap Reference
Bold items are power-up default conditions.
0
VREF = 2.5 V (RBG bit = 0)
1
VREF = 2.048 V (RBG bit = 0)
0
Bit R2V determines the value of the reference voltage.
1
VREF = 1.15 V
Figure 31. Reference/Oscillator Configuration Register (ADDR = 7)
D0
RBG
Oscillator Control
The internal voltage reference uses a switched capacitor technique which requires a clocking signal input.
When OSCR = 1, the clocking signal for the reference comes from the internal oscillator. When OSCR = 0, the
clocking signal for the reference is derived from the signal on the CCLK pin and affected by the frequency divider
controlled by the CFD0 and CFD1 bits in the A/D Control register.
The OSCE bit is the internal oscillator enable bit. When it is set to 1, power is applied to the internal oscillator
causing it to produce a 2.5-MHz output and causing the signal to appear at the CCLK pin. The internal oscillator
is also enabled when the OSCR bit and the REFE bit are set to 1, but does not make CCLK an output pin.
The internal oscillator is also enabled when the OSC ENABLE pin is set to 1. The power-up default condition
is 0 for OSCE and OSCR. If either the OSC ENABLE pin is held high, or either of these control register bits
are 1, then the oscillator is turned on.
Voltage Reference and Buffer Enable
When the REFE bit = 0 (power-up default condition), the reference is powered down and draws no current.
When REFE is set to 1, the reference is powered up and draws approximately 190 µA of current. When the
BUFE bit = 0 (power-up default condition), the buffer amplifier is powered down and draws no current. When
the buffer amplifier is set to 1, it is powered up and draws approximately 150 µA of current.
Selecting the Reference Voltage
When the RBG bit is set to 1, the voltage on the VREF pin is 1.15 V and the R2V bit has no effect. When this
bit is set to 0 (power-up default condition), the R2V bit determines the value of the reference voltage.
When R2V = 0 and RBG = 0 (power-up default condition), the voltage at the VREF pin is 2.5 V. When R2V =
1 and RBG = 0, the reference voltage is 2.048 V.
A 14-bit bipolar input A/D converter has 16384 states and each state corresponds to 305 µV with the 2.5-V
reference. With a 2.048-V reference, each A/D bit corresponds to 250 µV.
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