TMS320DM6441_101 Datasheet, PDF (34/232 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
Digital Media System-on-Chip
SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008
www.ti.com
Table 3-10. DDR2 Memory Controller Terminal Functions
SIGNAL
NAME
DDR_CLK0
DDR_CLK0
DDR_CKE
DDR_CS
DDR_WE
DDR_DQM[3]
DDR_DQM[2]
DDR_DQM[1]
DDR_DQM[0]
DDR_RAS
DDR_CAS
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
DDR_DQS[3]
DDR_BS[0]
DDR_BS[1]
DDR_BS[2]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
NO.
W7
W8
V8
T9
T8
T16
T14
T6
T4
U7
T7
U4
U6
U14
U16
U8
V9
U9
W9
W10
U10
U11
V10
V11
W11
W12
V12
U12
V13
U13
W13
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
OTHER ^{(2) (3)}
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DV_DDR2
DESCRIPTION
DDR2 Memory Controller
DDR2 clock
DDR2 differential clock
DDR2 clock enable
DDR2 active low chip select
DDR2 active low write enable
DDR2 data mask outputs
DQM3: For upper byte data bus DDR_D[31:24]
DQM2: For DDR_D[23:16]
DQM1: For DDR_D[15:8]
DQM0: For lower byte DDR_D[7:0]
DDR2 row access signal output
DDR2 column access signal output
Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to
the DDR2 memory when writing and inputs when reading. They are used to
synchronize the data transfers.
DQS3 : For upper byte DDR_D[31:24]
DQS2: For DDR_D[23:16]
DQS1: For DDR_D[15:8]
DQS0: For bottom byte DDR_D[7:0]
Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories.
DDR2 address bus
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
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