TMS320DM6441_101 Datasheet, PDF(205/232 Page) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6441_101 Datasheet, PDF (205/232 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6441

Digital Media System-on-Chip

SPRS359D â SEPTEMBER 2006 â REVISED MARCH 2008

Table 7-86. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS RANGE

01C8 012C

01C8 0130

01C8 0134

01C8 0138

01C8 013C

01C8 0140

01C8 0144

01C8 0148

01C8 014C

01C8 0150

01C8 0154

01C8 0158

01C8 015C

01C8 0160

01C8 0164

01C8 0168

01C8 016C

01C8 0170

01C8 0174

01C8 01D0

01C8 01D4

01C8 01D8

01C8 01DC

01C8 01E0

01C8 01E4

01C8 01E8

01C8 01EC

01C8 0200 - 01C8 02FC

01C8 0500

01C8 0504

01C8 0508

01C8 0600

01C8 0604

01C8 0608

01C8 060C

01C8 0610

01C8 0614

01C8 0618

01C8 061C

01C8 0620

01C8 0624

01C8 0628

01C8 062C

01C8 0630

01C8 0634

01C8 0638

01C8 063C

ACRONYM

RX3FLOWTHRESH

RX4FLOWTHRESH

RX5FLOWTHRESH

RX6FLOWTHRESH

RX7FLOWTHRESH

RX0FREEBUFFER

RX1FREEBUFFER

RX2FREEBUFFER

RX3FREEBUFFER

RX4FREEBUFFER

RX5FREEBUFFER

RX6FREEBUFFER

RX7FREEBUFFER

MACCONTROL

MACSTATUS

EMCONTROL

FIFOCONTROL

MACCONFIG

SOFTRESET

MACSRCADDRLO

MACSRCADDRHI

MACHASH1

MACHASH2

BOFFTEST

TPACETEST

RXPAUSE

TXPAUSE

(see Table 7-87)

MACADDRLO

MACADDRHI

MACINDEX

TX0HDP

TX1HDP

TX2HDP

TX3HDP

TX4HDP

TX5HDP

TX6HDP

TX7HDP

RX0HDP

RX1HDP

RX2HDP

RX3HDP

RX4HDP

RX5HDP

RX6HDP

RX7HDP

REGISTER NAME

Receive Channel 3 Flow Control Threshold Register

Receive Channel 4 Flow Control Threshold Register

Receive Channel 5 Flow Control Threshold Register

Receive Channel 6 Flow Control Threshold Register

Receive Channel 7 Flow Control Threshold Register

Receive Channel 0 Free Buffer Count Register

Receive Channel 1 Free Buffer Count Register

Receive Channel 2 Free Buffer Count Register

Receive Channel 3 Free Buffer Count Register

Receive Channel 4 Free Buffer Count Register

Receive Channel 5 Free Buffer Count Register

Receive Channel 6 Free Buffer Count Register

Receive Channel 7 Free Buffer Count Register

MAC Control Register

MAC Status Register

Emulation Control Register

FIFO Control Register (Transmit and Receive)

MAC Configuration Register

Soft Reset Register

MAC Source Address Low Bytes Register (Lower 16-bits)

MAC Source Address High Bytes Register (Upper 32-bits)

MAC Hash Address Register 1

MAC Hash Address Register 2

Back Off Test Register

Transmit Pacing Algorithm Test Register

Receive Pause Timer Register

Transmit Pause Timer Register

EMAC Statistics Registers

MAC Address Low Bytes Register

MAC Address High Bytes Register

MAC Index Register

Transmit Channel 0 DMA Head Descriptor Pointer Register

Transmit Channel 1 DMA Head Descriptor Pointer Register

Transmit Channel 2 DMA Head Descriptor Pointer Register

Transmit Channel 3 DMA Head Descriptor Pointer Register

Transmit Channel 4 DMA Head Descriptor Pointer Register

Transmit Channel 5 DMA Head Descriptor Pointer Register

Transmit Channel 6 DMA Head Descriptor Pointer Register

Transmit Channel 7 DMA Head Descriptor Pointer Register

Receive Channel 0 DMA Head Descriptor Pointer Register

Receive Channel 1 DMA Head Descriptor Pointer Register

Receive Channel 2 DMA Head Descriptor Pointer Register

Receive Channel 3 DMA Head Descriptor Pointer Register

Receive Channel 4 DMA Head Descriptor Pointer Register

Receive Channel 5 DMA Head Descriptor Pointer Register

Receive Channel 6 DMA Head Descriptor Pointer Register

Receive Channel 7 DMA Head Descriptor Pointer Register

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Peripheral and Electrical Specifications 205

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