ADS6149 Datasheet, PDF (34/70 Pages) Texas Instruments – 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs

ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS - ADS6148 (continued)
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V_PP
differential clock amplitude, 50% clock duty cycle, –1 DBFS differential analog input, internal reference mode, 0 dB gain,
LVDS output interface (unless otherwise noted)
100
95
90
85
80
75
70
65
60
55
50
0
SFDR
vs
INPUT FREQUENCY
LVDS
CMOS
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G026
Figure 38.
100
95
90
85
80
75
70
65
60
55
50
0
SFDR
vs
GAIN
Input adjusted to get −1dBFS input
3 dB
4 dB
5 dB
6 dB
2 dB
1 dB
0 dB
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G028
Figure 40.
74
73
72
71
70
69
68
67
66
65
64
0
SNR
vs
INPUT FREQUENCY
LVDS
CMOS
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G027
Figure 39.
SINAD
vs
GAIN
75
73
2 dB
3 dB
71
69
67
65
63
4 dB
5 dB
61
6 dB
59
1 dB
57 _{Input adjusted to get −1dBFS input}
0 dB
55
0 50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G029
Figure 41.
34
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