MSP430X11X2 Datasheet, PDF (31/47 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x11x2, MSP430x12x2
MIXED SIGNAL MICROCONTROLLER
SLAS361D − JANUARY 2002 − REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x
P1DIR.x
Direction Control
From Module
P1OUT.x
Module X OUT
0
1
0
Pad Logic
1
P1.4−P1.7
P1IN.x
Module X IN
P1IRQ.x
TST
EN
D
P1IE.x
P1IFG.x
EN
Q
Set
Interrupt
Flag
Interrupt
Edge
Select
P1IES.x
P1SEL.x
TDO
Controlled By JTAG
Bus Keeper
DV_CC
60 kΩ
Typical
TEST
Control by
JTAG
Bum
and
Test Fuse
P1.x
Controlled by JTAG
TDI
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
TMS
external pulldown resistor in some applications.
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
TCK
input for JTAG circuitry.
P1.7/TA2/TDO/TDI
TST
P1.x
P1.6/TA1/TDI/TCLK
TST
P1.x
P1.5/TA0/TMS
TST
P1.x
P1.4/SMCLK/TCK
DIRECTION
PnSel.x PnDIR.x CONTROL
FROM MODULE
P1Sel.4 P1DIR.4
P1DIR.4
P1Sel.5 P1DIR.5
P1DIR.5
P1Sel.6 P1DIR.6
P1DIR.6
P1Sel.7 P1DIR.7
P1DIR.7
† _{Signal from or to Timer_A}
PnOUT.x
P1OUT.4
P1OUT.5
P1OUT.6
P1OUT.7
MODULE X OUT
SMCLK
Out0 signal^†
Out1 signal^†
Out2 signal^†
PnIN.x
P1IN.4
P1IN.5
P1IN.6
P1IN.7
MODULE X IN
unused
unused
unused
unused
PnIE.x PnIFG.x PnIES.x
P1IE.4
P1IE.5
P1IE.6
P1IE.7
P1IFG.4
P1IFG.5
P1IFG.6
P1IFG.7
P1IES.4
P1IES.5
P1IES.6
P1IES.7
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