TMS44409 Datasheet, PDF (3/26 Pages) Texas Instruments – 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

functional block diagram
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
RAS CAS W OE
Timing and Control
A0
A1
8
Column Decode
16
Column-
Address ²
Buffers
A9
Sense Amplifiers
128K Array
128K Array
R
o
w
128K Array
128K Array
16
I/O
Buffers
Data-
In
4
Reg.
16
Row-
Address
Buffers
10
D
e
c
o
d
e
16
4 of 16
Selection
Data- ⁴
Out
Reg.
DQ1 – DQ4
2
128K Array
128K Array
10
operation
extended data out
Extended data out allows for data output rates of up to 40 MHz for 60-ns devices. When keeping the same row
address while selecting random column addresses, the time for row-address setup and hold and address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by t_RASP , the
maximum RAS low time.
Extended data out does not place the DQs into the high-impedance state with the rising edge of CAS. The output
remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE
and W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation
benefit.
address ( A0– A9)
Twenty address bits are required to decode one of 1 048 576 storage cell locations. Ten row-address bits are
set up on A0 through A9 and latched onto the chip by the row-address strobe ( RAS). The ten column-address
bits are set up on pins A0 through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip-enable in
that it activates the sense amplifiers as well as the row decoder.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two
methods for placing the DQs into the high-impedance state and keeping them that way during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for t_CHO past the CAS
transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second
method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of t_OEP anytime during
CAS high time, thus, disabling the DQs regardless of further transitions on OE until CAS falls again (see
Figure 7).
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