TMS418160A Datasheet, PDF (3/24 Pages) Texas Instruments – 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY

functional block diagram
TMS418160A
1048576 BY 16-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997
RAS UCAS LCAS W OE
Timing and Control
A0
A1
10
Column Decode
Column -
Sense Amplifiers
32
Address
Buffers
A9
256K Array
256K Array ^R
o
w
256K Array
256K Array
32
I/O
Buffers
Data- ₁₆
In
Reg.
16 of 32
16
Row -
Address
Buffers
32
10
D
e
c
o
32
Selection
Data-
Out
Reg.
d
DQ0 – DQ15
256K Array e 256K Array
10
operation
dual xCAS
Two xCAS pins (LCAS and UCAS) are provided to give independent control of the 16 data I/O pins
(DQ0– DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. Each xCAS
going low enables its corresponding DQx pin.
In write cycles, data-in setup and hold time (t_DS and t_DH) and write-command setup and hold time (t_WCS, t_CWL
and t_WCH) must be satisfied for each individual xCAS to ensure writing into the storage cells of the corresponding
DQ pins.
Different modes of operation for upper and lower bytes in one cycle are not allowed, such as the example shown
in Figure 1.
RAS
UCAS
Delayed write
LCAS
Early write
W
Figure 1. Illegal Dual-xCAS Operation
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