TL331-EP_15 Datasheet, PDF (3/11 Pages) Texas Instruments – SINGLE DIFFERENTIAL COMPARATOR

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TL331-EP
SLVSBU6 – JUNE 2013
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
TL331-EP
DBV
5 PINS
299
65.4
97.1
0.8
95.5
N/A
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, V_CC = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS⁽¹⁾
V_IO Input offset voltage
V_CC = 5 V to 30 V, V_O = 1.4 V,
V_IC = V_IC(min)
T_A
25°C
–55°C to 125°C
MIN TYP MAX UNIT
2
5
mV
9
I_IO
Input offset current
V_O = 1.4 V
25°C
–55°C to 125°C
5
50
nA
250
I_IB
Input bias current
V_O = 1.4 V
25°C
–55°C to 125°C
–25 –250
nA
–400
V_ICR
Common-mode input voltage
range ⁽²⁾
A_VD
Large-signal differential-voltage
amplification
V_CC = 15 V, V_O = 1.4 V to 11.4 V,
R_L ≥ 15 kΩ to V_CC
I_OH High-level output current
V_OH = 5 V, V_ID = 1 V
V_OH = 30 V, V_ID = 1 V
V_OL Low-level output voltage
I_OL = 4 mA, V_ID = –1 V
25°C
–55°C to 125°C
0 to
V_CC – 1.5
0 to
V_CC – 2
25°C
50 200
V
V/mV
25°C
–55°C to 125°C
25°C
–55°C to 125°C
0.1
50 nA
1 μA
150 400
mV
700
I_OL
Low-level output current
I_CC
Supply current
V_OL = 1.5 V, V_ID = –1 V
R_L = ∞, V_CC = 5 V
25°C
25°C
6
mA
0.4 0.7 mA
(1) All characteristics are measured with zero common-mode input voltage, unless otherwise specified.
(2) The voltage at either input or common-mode should not be allowed to go negative by more than 0.3 V. The upper end of the common-
mode voltage range is V_CC+ – 1.5 V, but either or both inputs can go to 30 V without damage.
Copyright © 2013, Texas Instruments Incorporated
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