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TL16C450 Datasheet, PDF (3/25 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT
block diagram
D7 – D0 1– 8
Data
Bus
Buffer
Internal
Data Bus
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B – MARCH 1988 – REVISED MARCH 1996
Receiver
Buffer
Register
Receiver
Shift
Register
10 SIN
Line
Control
Register
Divisor
Latch (LS)
A0 28
A1 27
A2 26
CS0 12
CS1 13
CS2 14
ADS 25
MR 35
DISTR 22
DISTR 21
DOSTR 19
DOSTR 18
DDIS 23
CSOUT 24
XTAL1 16
XTAL2 17
Select
and
Control
Logic
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
40
VCC 20
VSS
Power
Supply
Terminal numbers shown are for the N package.
Interrupt
Enable
Register
Interrupt
I/O
Register
Baud
Generator
Interrupt
Control
Logic
Receiver
Timing and
Control
9 RCLK
15 BAUDOUT
Transmitter
Timing and
Control
Transmitter
Shift
Register
11 SOUT
Modem
Control
Logic
32 RTS
36 CTS
33 DTR
37 DSR
38 DCD
39 RI
34 OUT1
31 OUT2
30
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