TL16C450 Datasheet, PDF (16/25 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B – MARCH 1988 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
O DLAB = 0 O DLAB = 0 1 DLAB = 0
2
3
4
Bit
No.
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write
Only)
Interrupt
Enable
Register
IER
Interrupt
Ident.
Register
(Read
Only)
Line
Control
Register
LCR
Modem
Control
Register
RBR
THR
IER
IIR
LCR
MCR
Enable
Word
0
Data Bit 0* Data Bit 0
Received
Data
Available
Interrupt
“0” If
Interrupt
Pending
Length
Select
Bit 0
(WLSO)
Data
Terminal
Ready
(DTR)
(ERBF)
Enable
Transmitter
Word
Holding
Interrupt Length Request
1
Data Bit 1
Data Bit 1
Register
ID
Select
to Send
Empty
Bit (0)
Bit 1
(RTS)
Interrupt
(WLS1)
(ETBE)
Enable
Receiver
Interrupt Number of
2
Data Bit 2
Data Bit 2 Line Status
ID
Stop Bits
Out 1
Interrupt
Bit (1)
(STB)
(ELSI)
Enable
Modem
3
Data Bit 3
Data Bit 3
Status
Interrupt
(EDSSI)
Parity
0
Enable
Out 2
(PEN)
5
Line
Status
Register
LSR
Data
Ready
(DR)
Overrun
Error
(OE)
Parity
Error
(PE)
Framing
Error
(FE)
1
6
7
O DLAB = 1 DLAB
=0
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Latch
(MSB)
MSR
SCR
DLL
DLM
Delta
Clear
to Send
(DCTS)
Bit 0
Bit 0
Bit 8
Delta
Data
Set
Ready
(DDSR)
Bit 1
Trailing
Edge Ring
Indicator
(TERI)
Delta
Data
Carrier
Detect
(DDCD)
Bit 2
Bit 3
Bit 1
Bit 9
Bit 2
Bit 10
Bit 3
Bit 11
4
Data Bit 4
Data Bit 4
0
Even
0
Parity
Select
Loop
Break
Interrupt
Clear
to Send
Bit 4
Bit 4
Bit 12
(EPS)
(BI)
(CTS)
5
Data Bit 5
Data Bit 5
0
Stick
0
Parity
0
6
Data Bit 6
Data Bit 6
0
Set
0
Break
0
7
Data Bit 7
Data Bit 7
0
Divisor
Latch
0
Access
0
Bit
(DLAB)
*Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Transmitter
Holding
Register
(THRE)
Transmitter
Empty
(TEMT)
0
Data
Set
Ready
(DSR)
Ring
Indicator
(RI)
Data
Carrier
Detect
(DCD)
Bit 5
Bit 6
Bit 7
Bit 5
Bit 13
Bit 6
Bit 14
Bit 7
Bit 15
16
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