TIL306 Datasheet, PDF (3/9 Pages) Texas Instruments – NUMERIC DISPLAYS WITH LOGIC

TIL306, TIL307
NUMERIC DISPLAYS WITH LOGIC
SLBS001 – D1034, JUNE 1982 – REVISED SEPTEMBER 1992
description
These internally-driven seven-segment light-emitting-diode (LED) displays contain a BCD counter, a four-bit
latch, and a decoder/LED driver in a single 16-pin package. A description of the functions of the inputs and
outputs of these devices are in the terminal function table.
The TTL MSI circuits contain the equivalent of 86 gates on a single chip. Logic inputs and outputs are completely
TTL/DTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases
of the input transistors to lower drive-current requirements to one-half of that required for a standard Series
54/74 TTL input. The serial-carry input, actually two internal loads, is rated as one standard series 54/74 load.
The logic outputs, except RBO, are active pullup, and the latch outputs Q_A, Q_B, Q_C, and Q_D are each capable
of driving three standard Series 54/74 loads at a low logic level or six loads at a high logic level while the
maximum-count output is capable of driving five Series 54/74 loads at a low logic level or ten loads at a high
logic level. The RBO node with passive pull-up serves as a ripple-blanking output with the capability to drive
three Series 54/74 loads.
The LED driver outputs are designed specifically to maintain a relatively constant on-level current of
approximately 7 mA through each LED segment and decimal point. All inputs are diode clamped to minimize
transmission-line effects, thereby simplifying system design. Maximum clock frequency is typically 18 MHz and
power dissipation is typically 600 mW with all segments on.
The display format is as follows:
The displays may be interconnected to produce an n-digit display with the following features:
• Ripple-blanking input and output for blanking leading or trailing zeroes
• Floating-decimal-point logic capability
• Overriding blanking for suppressing entire display or pulse modulation of LED brightness
• Dual count-enable inputs for parallel lookahead and serial ripple logic to build high-speed fully
synchronous, multidigit counter systems with no external logic, minimizing total propagation delay from
the clock to the last latch output
• Provision for ripple-count cascading between packages
• Positive-edge-triggered synchronous BCD counter
• Parallel BCD data outputs available to drive logic processors or remote slaved displays simultaneously
with data being displayed
• Latch strobe input allows counter to operate while a previous data point is displayed
• Reset-to-zero capability with clear input.
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