TCM38C17IDL Datasheet, PDF (3/22 Pages) Texas Instruments – QComboE FOUR-CHANNEL QUAD PCM COMBO

TCM38C17IDL
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
TERMINAL
NAME
NO.
AREF
2
0ANLGIN+
6
0ANLGIN –
5
1ANLGIN+
12
1ANLGIN –
11
2ANLGIN+
43
2ANLGIN –
44
3ANLGIN+
37
3ANLGIN –
38
ASEL
24
AVDD
46
AVSS
3
DVDD
20
DVDDPLL
21
DVSSPLL
23
DVSS
19
0FS
31
1FS
30
2FS
29
3FS
28
0GSR
8
1GSR
14
2GSR
41
3GSR
35
0GSX
4
1GSX
10
2GSX
45
3GSX
39
MCLK
22
PCMIN
25
PCMOUT
27
0PDN
16
1PDN
17
2PDN
32
Terminal Functions
SLWS040C – JUNE 1996 – REVISED OCTOBER 1999
I/O
DESCRIPTION
Analog reference point (mid-supply). This voltage is generated internally at a nominal 2.375 V. An
external decoupling capacitor (0.1 µF) should be connected from AREF to AVSS for filtering purposes.
I Noninverting analog input to uncommitted transmit operational amplifier for channel 0
I Inverting analog input to uncommitted transmit operational amplifier for channel 0
I Noninverting analog input to uncommitted transmit operational amplifier for channel 1
I Inverting analog input to uncommitted transmit operational amplifier for channel 1
I Noninverting analog input to uncommitted transmit operational amplifier for channel 2
I Inverting analog input to uncommitted transmit operational amplifier for channel 2
I Noninverting analog input to uncommitted transmit operational amplifier for channel 3
I Inverting analog input to uncommitted transmit operational amplifier for channel 3
I A-law and µ-law operation select. When ASEL is connected to ground, A-law is selected. When ASEL is
connected to VDD, µ-law is selected (digital).
Analog supply voltage, 5 V, ±5%
Analog ground return for AVDD supply
Digital supply voltage, 5 V, ±5%
Phase-locked loop supply voltage, 5 V, ±5%
Phase-locked loop ground return for DVDDPLL supply
Digital ground return for DVDD supply
I Frame synchronization clock input/time slot enable for channel 0 TX and RX (digital)
I Frame synchronization clock input/time slot enable for channel 1 TX and RX (digital)
I Frame synchronization clock input/time slot enable for channel 2 TX and RX (digital)
I Frame synchronization clock input/time slot enable for channel 3 TX and RX (digital)
I Receive amplifier gain-set input (channel 0). The ratio of an external voltage divider network connected to
0PWRO – and 0PWRO+ determines the receive amplifier gain. Maximum gain occurs when 0GSR is
connected to 0PWRO –, and minimum gain occurs when it is connected to 0PWRO+ (analog).
I Receive amplifier gain-set input (channel 1). The ratio of an external voltage divider network connected to
1PWRO – and 1PWRO+ determines the receive amplifier gain. Maximum gain occurs when 1GSR is
connected to 1PWRO –, and minimum gain occurs when it is connected to 1PWRO+ (analog).
I Receive amplifier gain-set input (channel 2). The ratio of an external voltage divider network connected to
2PWRO – and 2PWRO+ determines the receive amplifier gain. Maximum gain occurs when 2GSR is
connected to 2PWRO –, and minimum gain occurs when it is connected to 2PWRO+ (analog).
I Receive amplifier gain-set input (channel 3). The ratio of an external voltage divider network connected to
3PWRO – and 3PWRO+ determines the receive amplifier gain. Maximum gain occurs when 3GSR is
connected to 3PWRO –, and minimum gain occurs when it is connected to 3PWRO+ (analog).
O Output terminal of internal uncommitted transmit operational amplifier for channel 0 (analog)
O Output terminal of internal uncommitted transmit operational amplifier for channel 1 (analog)
O Output terminal of internal uncommitted transmit operational amplifier for channel 2 (analog)
O Output terminal of internal uncommitted transmit operational amplifier for channel 3 (analog)
I Master clock input (2.048 MHz) (digital)
I Transmit PCM input (digital)
O Transmit PCM output (digital)
I Power-down select for channel 0. This channel of the device is inactive with a CMOS low-level input to
0PDN and active with a CMOS high-level input to the terminal (digital).
I Power-down select for channel 1. This channel of the device is inactive with a CMOS low-level input to
1PDN and active with a CMOS high-level input to the terminal (digital).
I Power-down select for channel 2. This channel of the device is inactive with a CMOS low-level input to
2PDN and active with a CMOS high-level input to the terminal (digital).
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