TAS5142 Datasheet, PDF (3/26 Pages) Texas Instruments – STEREO DIGITAL AMPLIFIER POWER STAGE

TAS5142
www.ti.com
SLES126B – DECEMBER 2004 – REVISED MAY 2005
GENERAL INFORMATION (continued)
MODE Selection Pins for Both Packages
MODE PINS
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PWM INPUT
2N ⁽¹⁾ AD/BD modulation
Reserved
1N ⁽¹⁾ AD modulation
1N ⁽¹⁾ AD modulation
1N ⁽¹⁾ AD modulation
Reserved
OUTPUT CONFIGURATION
2 channels BTL output
PROTECTION SCHEME
BTL mode ⁽²⁾
2 channels BTL output
1 channel PBTL output
4 channels SE output
BTL mode ⁽²⁾
PBTL mode. Only PWM_A input is used.
Protection works similarly to BTL mode ⁽²⁾. Only
difference in SE mode is that OUT_X is Hi-Z
instead of a pulldown through internal pulldown
resistor.
(1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific
mode.
(2) An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors
like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
Package Heat Dissipation Ratings⁽¹⁾
PARAMETER
R_θJC (°C/W)—2 BTL or 4 SE channels (8 transistors)
R_θJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors)
R_θJC (°C/W)—(1 transistor)
Pad area⁽²⁾
TAS5142DKD
1.28
2.56
8.6
80 mm²
TAS5142DDV
1.28
2.56
8.6
36 mm²
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) R_θCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
R_θCH with this condition is 0.8°C/W for the DKD package and 1.8°C/W for the DDV package.
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