SN65LVDS122_07 Datasheet, PDF (3/21 Pages) Texas Instruments – 1.5-Gbps 2 ´ 2 LVDS CROSSPOINT SWITCH

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SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
V_IT+
V_IT-
V_ID(HYS)
I_IH
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential input voltage hysteresis (V_IT+– V_IT-)
DE
High-level input current
S0, S1
See Figure 1 and Table 1
See Figure 1 and Table 1
V_IH = 2
–100 ⁽²⁾
–10
0
100 mV
mV
25
mV
0
µA
20
DE
I_IL
Low-level input current
S0, S1
V_IL = 0.8 V
–10
0
µA
20
I_CC
Supply current
R_L = 100 Ω
Disabled
80 100
mA
35 45
Input current (A or B inputs 'LVDS)
I_I
Input current (A or B inputs 'LVDT)
Input current (A or B inputs 'LVDS)
I_I(OFF)
Input current (A or B inputs 'LVDT)
V_I = 0 V or 2.4 V, Other input at 1.2 V
–20
V_I = 4 V, Other input at 1.2 V
0
V_I = 0 V or 2.4 V, Other input open
–40
V_I = 4 V, Other input open
0
V_CC = 1.5 V, V_I = 0 V or 2.4 V,
Other input at 1.2 V
–20
V_CC = 1.5 V, V_I = 2.4 V or 4 V,
Other input at 1.2 V
0
V_CC = 1.5 V, V_I = 0 V or 2.4 V,
Other input open
–40
V_CC = 1.5 V, V_I = 2.4 V or 4 V,
Other input open
0
20
µA
33
40
µA
66
20
µA
33
40
µA
66
I_IO
Input offset current (| I_IA– I_IB |) 'LVDS
Termination resistance ('LVDT)
R_T
Termination resistance ('LVDT with power-off)
C_I
Differential input capacitance ('LVDT with
power-off)
V_IA = V_IB, 0 ≤ V_IA ≤ 4 V
V_ID = 300 mV and 500 mV,
V_IC = 0 V to 2.4 V
V_ID = 300 mV and 500 mV,
V_CC = 1.5 V, V_IC = 0 V to 2.4 V
V_I = 0.4 sin (4E6πt) + 0.5 V
Powered down (V_CC = 1.5 V)
–6
6 µA
90 110 132
Ω
90 110 132
3
pF
3
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
|V_OD|
∆|V_OD|
V_OC(SS)
∆V_OC(SS)
V_OC(PP)
I_OS
I_OS(D)
PARAMETER
Differential output voltage magnitude
Change in differential output voltage magnitude between logic
states
Steady-state common-mode output voltage
Change in steady-state common-mode output voltage between
logic states
Peak-to-peak common-mode output voltage
Short-circuit output current
Differential short-circuit output current
I_OZ
High-impedance output current
C_o
Differential output capacitance
(1) All typical values are at 25°C and with a 3.3-V supply.
TEST CONDITIONS
See Figure 2
See Figure 3
V_O(Y) or V_O(Z) = 0 V
V_OD = 0 V
V_OD = 600 mV
V_O = 0 V or V_CC
V_I = 0.4 sin (4E6πt) + 0.5 V
MIN TYP⁽¹⁾
247 310
–50
MAX
454
50
UNIT
mV
1.125
1.375 V
–50
50 mV
50 150 mV
–24
24 mA
–12
12 mA
–1
1
µA
–1
1
3
pF
3