SN65LVDS122_07 Datasheet, PDF (1/21 Pages) Texas Instruments – 1.5-Gbps 2 ´ 2 LVDS CROSSPOINT SWITCH

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SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
1.5-Gbps 2 × 2 LVDS CROSSPOINT SWITCH
FEATURES
• Designed for Signaling Rates ⁽¹⁾ Up To
1.5 Gbps
• Total Jitter < 65 ps
• Pin-Compatible With SN65LVDS22 and
SN65LVDM22
• 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
• Inputs Electrically Compatible With CML,
LVPECL and LVDS Signal Levels
• Propagation Delay Times, 900 ps Maximum
• LVDT Integrates 110-Ω Terminating Resistor
• Offered in SOIC and TSSOP
APPLICATIONS
• 10-G (OC-192) Optical Modules
• 622-MHz Central Office Clock Distribution
• Wireless Basestations
• Low Jitter Clock Repeater/Multiplexer
• Protection Switching for Serial Backplanes
(1) The signlaing rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
FUNCTIONAL DIAGRAM
1DE
DESCRIPTION
The SN65LVDS122 and SN65LVDT122 are
crosspoint switches that use low voltage differential
signaling (LVDS) to achieve signaling rates as high
as 1.5 Gbps. They are pin-compatible speed up-
grades to the SN65LVDS22 and SN65LVDM22. The
internal signal paths maintain differential signaling for
high speeds and low signal skews. These devices
have a 0-V to 4-V common-mode input range that
accepts LVDS, LVPECL, or CML inputs. Two logic
pins (S0 and S1) set the internal configuration be-
tween the differential inputs and outputs. This allows
the flexibility to perform the following configurations:
2 x 2 crosspoint switch, 2:1 input multiplexer, 1:2
splitter or dual repeater/translator within a single
device. Additionally, SN65LVDT122 incorporates a
110-Ω termination resistor for those applications
where board space is a premium. Although these
devices are designed for 1.5 Gbps, some applications
at a 2-Gbps data rate can be supported depending on
loading and signal quality.
The intended application of this device is ideal for
loopback switching for diagnostic routines, fanout
buffering of clock/data distribution provide protection
in fault-tolerant systems, clock multiplexing in optical
modules, and for overall signal boosting over
extended distances.
The SN65LVDS122 and SN65LVDT122 are
characterized for operation from –40°C to 85°C.
EYE PATTERNS OF OUTPUTS
OPERATING SIMULTANEOUSLY
1A
110 Ω
1B
S0
S1
MUX
1Y
1.5 Gbps
1Z
2²³ − 1 PRBS
V_CC = 3.3 V
V_ID = 200 mV, V_IC = 1.2 V
Vertical Scale=200 mV/div
2A
2Y
110 Ω
2Z
2B
2DE
Integrated Termination on SN65LVDT122 Only
OUTPUT 1
OUTPUT 2
Horizontal Scale= 200 ps/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated