SM72295_15 Datasheet, PDF (3/17 Pages) Texas Instruments – SM72295 Photovoltaic Full Bridge Driver

SM72295
www.ti.com
SNVS688E – OCTOBER 2010 – REVISED APRIL 2013
Pin
19, 27
20,26
21,25
22, 24
23
PIN DESCRIPTIONS (continued)
Name
HOA,
HOB
HBA,
HBB
VCCA,
VCCB
LOA,
LOB
PGND
Description
High side gate driver output
Application Information
Connect to gate of high side MOSFET with a short low inductance path.
High side gate driver bootstrap rail. Connect the positive terminal of the bootstrap capacitor to HB and the negative
terminal to HS. The bootstrap capacitor should be placed as close to IC as
possible.
Positive gate drive supply
Locally decouple to PGND using low ESR/ESL capacitor located as close to IC
as possible.
Low side gate driver output
Connect to the gate of the low side MOSFET with a short low inductance path.
Power ground return
Ground return for the LO drivers. Tie to the ground plane under the IC
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings⁽¹⁾⁽²⁾
VCCA, VCCB
VDD
HBA to HSA, HBB to HSB
LIA,LIB,HIA,HIB,OVS
LOA,LOB
HOA,HOB
SIA,SOA,SIB,SOB
SIA to SOA, SIB to SOB
HSA,HSB ⁽³⁾
HBA, HBB
PGOOD, OVP
IIN, IOUT
BIN, BOUT
Junction Temperature
Storage Temperatue Range
ESD Rating⁽⁴⁾
Human Body Model
-0.3 to 14V
-0.3 to 7V
-0.3 to 15V
-0.3 to 7V
-0.3 to VCC+ 0.3V
HS–0.3 to HB + 0.3V
-0.3 to 100V
-0.8 to 0.8V
-5 to 100V
115V
-0.3 to VDD
-0.3 to VDD
-0.3 to VDD
150°C
-55°C to +150°C
2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally
not exceed –1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur, the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V,
the negative transients at HS must not exceed –5V.
(4) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV for all pins except HB, HO & HS
which are rated at 1000V.
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