LP3873_15 Datasheet, PDF (3/24 Pages) Texas Instruments – 3A Fast Ultra Low Dropout Linear Regulators

www.ti.com
Block Diagram LP3876
LP3873, LP3876
SNVS220E – NOVEMBER 2002 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings⁽¹⁾⁽²⁾
Storage Temperature Range
−65°C to +150°C
Lead Temperature
ESD Rating⁽³⁾
Power Dissipation⁽⁴⁾
Soldering, 5 sec.
260°C
2 kV
Internally Limited
Input Supply Voltage (Survival)
−0.3V to +7.5V
Shutdown Input Voltage (Survival)
Output Voltage (Survival)⁽⁵⁾⁽⁶⁾
−0.3V to 7.5V
−0.3V to +6.0V
I_OUT (Survival)
Maximum Voltage for ERROR Pin
Maximum Voltage for SENSE Pin
Short Circuit Protected
V_IN
V_OUT
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
(4) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be
derated at θ_jA = 50°C/W (with 0.5in², 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-
mount package must be derated at θ_jA = 60°C/W (with 0.5in², 1oz. copper area), junction-to-ambient. See Application Hints.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
(6) The output PMOS structure contains a diode between the V_IN and V_OUT terminals. This diode is normally reverse biased. This diode will
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can
typically withstand 200mA of DC current and 1Amp of peak current.
Operating Ratings
Input Supply Voltage⁽¹⁾
Shutdown Input Voltage
Maximum Operating Current (DC)
Junction Temperature
(1) The minimum operating value for V_IN is equal to either [V_OUT(NOM) + V_DROPOUT] or 2.5V, whichever is greater.
2.5V to 7.0V
−0.3V to 7.0V
3A
−40°C to +125°C
Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: LP3873 LP3876
Submit Documentation Feedback
3