DS91C176TMAX-NOPB Datasheet, PDF (3/19 Pages) Texas Instruments – DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers

DS91C176, DS91D176
www.ti.com
SNLS146L – MARCH 2006 – REVISED APRIL 2013
Absolute Maximum Ratings ⁽¹⁾⁽²⁾
Supply Voltage, V_CC
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
Receiver Input Voltages
Receiver Output Voltage
Maximum Package Power Dissipation at +25°C
SOIC Package
Derate SOIC Package
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
θ_JA
θ_JC
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 seconds)
ESD Ratings:
(HBM 1.5kΩ, 100pF)
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
−0.3V to +4V
−0.3V to (V_CC + 0.3V)
−0.3V to (V_CC + 0.3V)
−1.8V to +4.1V
−1.8V to +4.1V
−0.3V to (V_CC + 0.3V)
833 mW
6.67 mW/°C above +25°C
150°C/W
63°C/W
150°C
−65°C to +150°C
260°C
≥ 8 kV
≥ 250 V
≥ 1000 V
(1) “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be verified. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
Supply Voltage, V_CC
Voltage at Any Bus Terminal (Separate or Common-Mode)
Differential Input Voltage V_ID
LVTTL Input Voltage High V_IH
LVTTL Input Voltage Low V_IL
Operating Free Air Temperature T_A
Min Typ Max Units
3.0 3.3 3.6
V
−1.4
+3.8 V
2.4
V
2.0
V_CC
V
0
0.8
V
−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. ^{(1) (2) (3) (4)}
Parameter
Test Conditions
Min Typ Max Units
M-LVDS Driver
|V_AB|
ΔV_AB
Differential output voltage magnitude
Change in differential output voltage magnitude
between logic states
R_L = 50Ω, C_L = 5pF
See Figure 4 and Figure 6
480
650 mV
−50
0
+50 mV
V_OS(SS)
|ΔV_OS(SS)|
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
R_L = 50Ω, C_L = 5pF
See Figure 4 and Figure 5
(V_OS(PP) @ 500KHz clock)
0.3 1.8 2.1
V
0
+50 mV
V_OS(PP)
V_A(OC)
V_B(OC)
Peak-to-peak common-mode output voltage
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
See Figure 7
135
mV
0
2.4
V
0
2.4
V
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
(2) All typicals are given for V_CC = 3.3V and T_A = 25°C.
(3) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
(4) C_L includes fixture capacitance and C_D includes probe capacitance.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS91C176 DS91D176