DRV8834 Datasheet, PDF (3/30 Pages) Texas Instruments – DUAL BRIDGE STEPPER OR DC MOTOR DRIVER

DRV8834
www.ti.com
SLVSB19A – FEBRUARY 2012 – REVISED MARCH 2012
Table 1. TERMINAL FUNCTIONS
NAME
PIN
(PWP)
POWER AND GROUND
GND
21,
PPAD
PIN
(RGE)
18,
PPAD
VM
18, 19 15, 16
I/O ⁽¹⁾
-
-
VINT
20
17
-
VREFO
24
21
O
VCP
17
14
O
CONTROL (Indexer Mode or Phase/Enable Mode)
nENBL/AENBL 10
7
I
STEP/BENBL
11
8
I
DIR/BPHASE
12
9
I
M0/APHASE
13
10
I
M1
14
11
I
CONFIG
15
12
I
nSLEEP
1
22
I
AVREF
22
19
I
BVREF
23
20
I
ADECAY
3
24
I
BDECAY
2
23
I
DESCRIPTION
Device ground
Bridge A power supply
Internal supply
Reference voltage output
High-side gate drive voltage
Step motor enable/Bridge A enable
Step input/Bridge B enable
Direction input/Bridge B Phase
Microstep mode/Bridge A phase
Microstep mode/Disable state
Device configuration
Sleep mode input
Bridge A current set reference input
Bridge B current set reference input
Decay mode for bridge A
Decay mode for bridge B
EXTERNAL COMPONENTS
OR CONNECTIONS
Both the GND pin and device PowerPAD
must be connected to ground
Connect to motor supply. A 10-µF (minimum)
capacitor to GND is recommended.
Bypass to GND with 2.2-μF (minimum), 6.3-V
capacitor. Can be used to provide logic high
voltage for configuration pins (except
nSLEEP).
May be connected to AVREF/BVREF inputs.
Do not place a bypass capacitor on this pin.
Connect a 0.01-μF, 16-V (minimum) X7R
ceramic capacitor to VM.
Indexer mode: Logic low enables all outputs.
Phase/enable mode: Logic low enables the
AOUTx outputs.
Internal pulldown.
Indexer mode: Rising edge moves indexer to
next step.
Phase/enable mode: Logic low enables the
BOUTx outputs.
Internal pulldown.
Indexer mode: Level sets direction of step.
Phase/enable mode: Logic high sets BOUT1
high, BOUT2 low.
Internal pulldown.
Indexer mode: Controls microstep mode (full,
half, up to 1/32-step) along with M1.
Phase/enable mode: Logic high sets AOUT1
high, AOUT2 low.
Internal pulldown.
Indexer mode: Controls microstep mode (full,
half, up to 1/32-step) along with M0.
Phase/enable mode: Determines the state of
the outputs when xENBL = 0.
Internal pulldown.
Logic high to put the device in indexer mode.
Logic low to put the device into phase/enable
mode. State is latched at power-up and sleep
exit. Internal pulldown.
Logic high to enable device, logic low to
enter low-power sleep mode and reset all
internal logic.
Reference voltage for winding current set.
Can be driven individually with an external
DACs for micro-stepping, or tied to a
reference voltage (e.g., VREFO).
Reference voltage for winding current set.
Can be driven individually with an external
DACs for micro-stepping, or tied to a
reference voltage (e.g., VREFO).
Determines decay mode for H-Bridge A (or A
and B in indexer mode) – slow, fast or mixed
decay
Determines decay mode for H-Bridge B –
slow, fast or mixed decay
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DRV8834
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