CD54ACT109_08 Datasheet, PDF (3/11 Pages) Texas Instruments – DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT109, CD74ACT109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS327 – JANUARY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN MAX
–55°C to
125°C
MIN MAX
–40°C to
85°C
MIN MAX
UNIT
VOH
VI = VIH or VIL
VOL
II
ICC
DICC^‡
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
VI = VCC – 2.1 V
IOH = –50 µA
IOH = –24 mA
IOH = –50 mA^†
IOH = –75 mA^†
IOL = 50 µA
IOL = 24 mA
IOL = 50 mA^†
IOL = 75 mA^†
IO = 0
4.5 V
4.5 V
5.5 V
5.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.5 V to
5.5 V
4.4
4.4
4.4
3.94
3.7
3.8
V
3.85
3.85
0.1
0.1
0.1
0.36
0.5
0.44
V
1.65
1.65
±0.1
±1
±1 µA
4
80
40 µA
2.4
3
2.8 mA
Ci
10
10
10 pF
† _{Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize}
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
‡ _{Additional quiescent supply current per input pin, TTL inputs high, 1 unit load}
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD
J or CLK
1
K
0.53
CLR or PRE
0.58
Unit Load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
timing requirements over recommended operating conditions (unless otherwise noted)
fclock Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, after CLK↑
trec
Recovery time, before CLK↑
CLK high or low
CLR or PRE low
J or K
J or K
CLR↑ or PRE↑
–55°C to
125°C
MIN MAX
100
5
5.5
5.5
0
2.5
–40°C to
85°C
MIN MAX
114
4.4
4.8
4.8
0
2.2
UNIT
MHz
ns
ns
ns
ns
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