AM5K2E04_15 Datasheet, PDF (3/252 Pages) Texas Instruments – AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)

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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
The device enables developers to use a variety of development and debugging tools that include GNU
GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space
debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
1.5 Enhancements in KeyStone II
The KeyStone II architecture provides many major enhancements over the previous KeyStone I
generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core
cluster to enable Layer 2 (MAC/RLC) and higher layer processing. The external memory bandwidth has
been doubled with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is
quadrupled with MSMC V2 architecture improvements. Multicore Navigator supports 2× the number of
queues, descriptors and packet DMA, 4× the number of micro RISC engines and a significant increase in
the number of push/pops per second, compared to the previous generation. The new peripherals that
have been added include the USB 3.0 controller and Asynchronous EMIF controller for NAND/NOR
memory access. The 2-port Gigabit Ethernet switch in KeyStone I has been replaced with an 8-port
Gigabit Ethernet switch and a 10 GbE switch in KeyStone II. Time synchronization support has been
enhanced to reduce software workload and support additional standards like IEEE1588 Annex D/E and
SyncE. The number of GPIOs and serial interface peripherals like I²C and SPI have been increased to
enable more board level control functionality.
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AM5K2E0x Features and Description
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