AM5K2E04_15 Datasheet, PDF (212/252 Pages) Texas Instruments – AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)

AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
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The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on
reset, DDR3 PLL is programmed to a valid frequency during the boot configuration process before being
enabled and used.
DDR3 PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit
must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices application
report (SPRABV0) for detailed recommendations.
PLLM
DDR3 PLL
DDRCLK(N|P)
PLLD
VCO
0
CLKOD
1
BYPASS
PLLOUT
DDR3
PHY
´2
Figure 10-22. DDR3 PLL Block Diagram
DDR3CLKOUT
10.6.1 DDR3 PLL Control Registers
The DDR3 PLL, which is used to drive the DDR3 PHY for the EMIF, does not use a PLL controller. DDR3
PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg
module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these
registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For
suggested configurable values, see Section 8.1.4. See Section 8.2.3.4 for the address location of the
registers and locking and unlocking sequences for accessing the registers. These registers are reset on
POR only.
Figure 10-23. DDR3 PLL Control Register 0 (DDR3PLLCTL0)
31
24
23
22
19
18
6
BWADJ[7:0]
BYPASS
CLKOD
PLLM
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
5
0
PLLD
RW,+000000
Bit Field
31-24 BWADJ[7:0]
23
BYPASS
22-19 CLKOD
18-6 PLLM
5-0 PLLD
Table 10-28. DDR3 PLL Control Register 0 Field Descriptions
Description
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply
factor minus 1
A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide
value minus 1
212 AM5K2E0x Peripheral Information and Electrical Specifications
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