ADS54T04 Datasheet, PDF (3/44 Pages) Texas Instruments – Dual Channel 12-Bit 500Msps Receiver and Feedback IC

ADS54T04
www.ti.com
PINOUT INFORMATION
SLAS917 – DECEMBER 2012
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
VREF
VCM
GND
INB_N INB_P
GND AVDDC AVDDC GND
INA_P INA_N
GND
GND CLKINP
14
13
SDENB
TEST
MODE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND CLKINN
13
12
SCLK SRESET GND AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 GND AVDD33 AVDD33
12
11
SDIO ENABLE GND AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 GND AVDD18 AVDD18
11
10
SDO
IOVDD
GND AVDD18 GND
GND
GND
GND
GND
GND
AVDD18
GND
TRIGGER TRIGGER
N
P
10
9
DVDD DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND SYNCN SYNCP
9
8
DVDD DVDD DVDD DVDD
GND
GND
GND
GND
GND
GND
DVDD DVDD DVDD DVDD
8
7
DB0N
DB0P
DVDD
LVDS
DVDD
LVDS
GND
GND
GND
GND
GND
GND
DVDD
LVDS
DVDD
LVDS
TRDYN TRDYP
7
6
DB1N
DB1P
DVDD
LVDS
DVDD
LVDS
GND
GND
GND
GND
GND
GND
DVDD
LVDS
DVDD
LVDS
HRESN HRESP
6
5
DB2N
DB2P OVRBN OVRBP GND
GND
GND
GND
GND
GND
OVRAN OVRAP
SYNC
OUTN
SYNC
OUTP
5
4
DB3N
DB3P
DB8P DB10P
NC
HRESP TRDYP DA0P
DA2P
DA4P
DA6P
DA8P
NC
NC
4
3
DB4N
DB4P
DB8N DB10N
NC
HRESN TRDYN DA0N
DA2N
DA4N
DA6N
DA8N DA11N DA11P
3
2
DB5N
DB5P
DB7P
DB9P
DB11P
SYNC
OUTP
DBCLKP DACLKP
DA1P
DA3P
DA5P
DA7P DA10N DA10P
2
1
DB6N
DB6P
DB7N
DB9N
DB11N
SYNC
OUTN
DBCLKN DACLKN
DA1N
DA3N
DA5N
DA7N
DA9N
DA9P
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 2. Pinout in DDR output mode (top down view)
PIN
NAME
NUMBER
INPUT/REFERENCE
INA_P/N
K14, L14
INB_P/N
D14, E14
VCM
B14
VREF
CLOCK/SYNC
CLKINP/N
A14
P14, P13
SYNCP/N
P9, N9
CONTROL/SERIAL
SRESET
B12
PIN ASSIGNMENTS
I/O
DESCRIPTION
I Analog ADC A differential input signal.
I Analog ADC B differential input signal.
O
Output of the analog input common mode (nominally 1.9V). A 0.1μF capacitor to AGND is
recommended.
I Reference voltage input. A 0.1μF capacitor to AGND is recommended, but not required.
I Differential input clock
Synchronization input. Inactive if logic low. When clocked in a high state initially, this is used
I for resetting internal clocks and digital logic and starting the SYNCOUT signal. Internal 100Ω
termination.
I
Serial interface reset input. Active low. Initialized internal registers during high to low
transition. Asynchronous. Internal 50kΩ pull up resistor to IOVDD.
Copyright © 2012, Texas Instruments Incorporated
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