TMS320C6412AGNZ7 Datasheet, PDF (28/163 Pages) Texas Instruments – TMS320C6412 Fixed-Point Digital Signal Processor

Peripheral Register Descriptions
HEX ADDRESS RANGE
0200 0000
0200 0004
0200 0008
0200 000C
0200 0010
0200 0014 − 0200 001C
0200 0020
0200 0024
0200 0028
0200 002C
0200 0030
Table 1−5. Quick DMA (QDMA) and Pseudo Registers
ACRONYM
QOPT
QSRC
QCNT
QDST
QIDX
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
REGISTER NAME
QDMA options parameter register
QDMA source address register
QDMA frame count register
QDMA destination address register
QDMA index register
Reserved
QDMA pseudo options register
QDMA psuedo source address register
QDMA psuedo frame count register
QDMA destination address register
QDMA psuedo index register
HEX ADDRESS RANGE
01A0 0800 − 01A0 FF98
01A0 FF9C
01A0 FFA4
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
01A0 FFB8
01A0 FFBC
01A0 FFC0
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
01A0 FFF8
01A0 FFFC
01A1 0000 − 01A3 FFFF
Table 1−6. EDMA Registers (C64x)
ACRONYM
−
EPRH
CIPRH
CIERH
CCERH
ERH
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
PQSR
CIPRL
CIERL
CCERL
ERL
EERL
ECRL
ESRL
–
REGISTER NAME
Reserved
Event polarity high register
Channel interrupt pending high register
Channel interrupt enable high register
Channel chain enable high register
Event high register
Event enable high register
Event clear high register
Event set high register
Priority queue allocation register 0
Priority queue allocation register 1
Priority queue allocation register 2
Priority queue allocation register 3
Event polarity low register
Priority queue status register
Channel interrupt pending low register
Channel interrupt enable low register
Channel chain enable low register
Event low register
Event enable low register
Event clear low register
Event set low register
Reserved
28 SPRS219J
April 2003 − Revised October 2010