TMS320C6412AGNZ7 Datasheet, PDF (147/163 Pages) Texas Instruments – TMS320C6412 Fixed-Point Digital Signal Processor

Ethernet Media Access Controller (EMAC) Timing
Table 16−3. Timing Requirements for EMAC MII Receive 10/100 Mbit/s^† (see Figure 16−3)
−500
−600
NO.
−720
MIN MAX
1 t_{su(MRXD-MRCLKH)}
Setup time, receive selected signals valid before MRCLK high
8
2 t_{h(MRCLKH-MRXD)}
Hold time, receive selected signals valid after MRCLK high
8
† _{Receive selected signals include: MRXD3−MRXD0, MRXDV, and MRXER.}
UNIT
ns
ns
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 16−3. EMAC Receive Interface Timing
Table 16−4. Switching Characteristics Over Recommended Operating Conditions for EMAC
MII Transmit 10/100 Mbit/s^‡ (see Figure 16−4)
−500
−600
NO.
−720
UNIT
1 t_{d(MTCLKH-MTXD)}
Delay time, MTCLK high to transmit selected signals valid
‡ _{Transmit selected signals include: MTXD3−MTXD0, and MTXEN.}
MIN MAX
5
25 ns
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 16−4. EMAC Transmit Interface Timing
April 2003 − Revised October 2010
SPRS219J 147