DAC7750_15 Datasheet, PDF (28/53 Pages) Texas Instruments – DACx750 Single-Channel, 12- and 16-Bit Programmable Current Output Digital-to-Analog Converters for 4-mA to 20-mA Current Loop Applications

DAC7750, DAC8750
SBAS538A – DECEMBER 2013 – REVISED MARCH 2014
www.ti.com
7.3.11 Frame Error Checking
In noisy environments, error checking can be used to check the integrity of SPI data communication between the
DACx750 and the host processor. To enable this feature, set the CRCEN bit of the Configuration Register to 1.
The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x⁸ + x² + x + 1 (that is,
100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in Table 6. Start with the
default 24-bit frame, enable frame error checking, and then switch to the 32-bit frame. The normal 24-bit SPI
data are appended with an 8-bit CRC polynomial by the host processor before feeding to the device. For a
register readback, the CRC polynomial is output on the SDO terminals by the device as part of the 32-bit frame.
Table 6. SPI Frame with Frame Error Checking Enabled
BIT 31:BIT 8
Normal SPI frame data
BIT 7:BIT 0
8-bit CRC polynomial
The DACx750 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in the frame,
the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or multiple-bit
errors), the ALARM terminal asserts low and the CRC-FLT bit of the status register is set to 1. The ALARM
terminal can be asserted low for any of the different conditions as explained in the Alarm Detection section. The
CRC-FLT bit is reset to 0 with a software reset, by disabling the frame error checking, or by powering down the
device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.
Frame error checking can be enabled for any number of DACx750 devices connected in a daisy-chain
configuration. However, it is recommended to enable error checking for either none or all devices in the chain.
When connecting the ALARM terminals of multiple devices, forming a wired-AND function, the host processor
reads the status register of each device to know all the fault conditions present in the chain. For proper
operation, the host processor must provide the correct number of SCLK cycles in each frame, taking care to
identify whether or not error checking is enabled in each device in the daisy-chain.
7.3.12 User Calibration
The device implements a user-calibration function (enabled by the CALEN bit in the Configuration Register) to
trim system gain and zero errors. The DAC output is calibrated according to the value of the gain calibration and
zero calibration registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The
gain register must be programmed to 0x8000 to achieve the default gain of 1 because the power-on value of the
register is 0x0000, equivalent to a gain of 0.5. The zero code adjustment is typically ±32,768 LSBs with 1 LSB
per step. The input data format of the gain register is unsigned straight binary, and the input data format of the
zero register is twos complement. The gain and offset calibration is described by Equation 4:
CODE _ OUT
= CODE
•
User _ GAIN + 2¹⁵
2¹⁶
+ User _ ZERO
where
•
•
•
•
•
CODE is the decimal equivalent of the code loaded to the DAC data register at address 0x01.
N is the bits of resolution; 16 for DAC8750 and 12 for DAC7750.
User_ZERO is the signed 16-bit code in the zero register.
User_GAIN is the unsigned 16-bit code in the gain register.
CODE_OUT is the decimal equivalent of the code loaded to the DAC (limited between 0x0000 to 0xFFFF for
DAC8750 and 0x000 to 0xFFF for DAC7750).
(4)
This is a purely digital implementation and the output is still limited by the programmed value at both ends of the
current output range (set by the RANGE bits, as described in the Setting Current-Output Ranges section). In
addition, the correction only makes sense for endpoints inside of the true device end points. To correct more
than just the actual device error, for example a system offset, the valid range for the adjustment changes
accordingly and must be taken into account.
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