TMS320F2810_11 Datasheet, PDF (27/170 Pages) Texas Instruments – Digital Signal Processors

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3 Functional Overview
TINT0
TINT1
XINT13
G
P
I
GPIO Pins ^O
M
U
X
XNMI
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
TINT2
PIE
(96 Interrupts)^(A)
External Interrupt
Control
(XINT1/2/13, XNMI)
SCIA/SCIB
SPI
McBSP
FIFO
FIFO
FIFO
eCAN
EVA/EVB
16 Channels
12-Bit ADC
XRS
X1/XCLKIN
X2
XF_XPLLDIS
System Control
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power Modes
+
Watchdog)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174S – APRIL 2001 – REVISED MARCH 2011
Memory Bus
INT14
INT[12:1]
INT13
NMI
C28x CPU
RS
CLKIN
Memory Bus
Peripheral Bus
Real-Time JTAG
External
Interface
(XINTF)^(B)
Control
Address (19)
Data (16)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
L0 SARAM
4K x 16
L1 SARAM
4K x 16
Flash
128K x 16 (F2812)
128K x 16 (F2811)
64K x 16 (F2810)
ROM
128K x 16 (C2812)
128K x 16 (C2811)
64K x 16 (C2810)
OTP^(C)
1K x 16
H0 SARAM
8K x 16
Boot ROM
4K x 16
Protected by the code-security module.
A. 45 of the possible 96 interrupts are used on the devices.
B. XINTF is available on the F2812 and C2812 devices only.
C. On C281x devices, the OTP is replaced with a 1K x 16 block of ROM.
Figure 3-1. Functional Block Diagram
Copyright © 2001–2011, Texas Instruments Incorporated
Functional Overview
27
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