TMS320F2810_11 Datasheet, PDF (103/170 Pages) Texas Instruments – Digital Signal Processors

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.14.2 Output Clock Characteristics
Table 6-10. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)⁽¹⁾⁽²⁾
NO.
PARAMETER
MIN
C1 t_c(XCO)
Cycle time, XCLKOUT
6.67 ⁽³⁾
C3 t_f(XCO)
Fall time, XCLKOUT
C4 t_r(XCO)
Rise time, XCLKOUT
C5 t_w(XCOL)
Pulse duration, XCLKOUT low
H–2
C6 t_w(XCOH)
C7 t_p
Pulse duration, XCLKOUT high
PLL lock time⁽⁴⁾
H–2
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5t_c(XCO)
(3) The PLL must be used for maximum frequency operation.
(4) This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
TYP
2
2
MAX
H+2
H+2
131072t_c(CI)
UNIT
ns
ns
ns
ns
ns
ns
C8
XCLKIN^(A)
C10
C9
C3
C6
C1
C4
C5
XCLKOUT^(A)(B)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
Figure 6-10 is intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-10. Clock Timing
6.15 Reset Timing
Table 6-11. Reset (XRS) Timing Requirements⁽¹⁾
MIN
NOM
MAX UNIT
t_w(RSL1)
t_w(RSL2)
t_w(WDRS)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Pulse duration, reset pulse generated by
watchdog
Warm reset
8t_c(CI)
8t_c(CI)
512t_c(CI)
cycles
cycles
cycles
t_d(EX)
t_OSCST ⁽²⁾
t_su(XPLLDIS)
t_h(XPLLDIS)
t_h(XMP/MC)
t_h(boot-mode)
Delay time, address/data valid after XRS
high
Oscillator start-up time
Setup time for XPLLDIS pin
Hold time for XPLLDIS pin
Hold time for XMP/MC pin
Hold time for boot-mode pins
1
16t_c(CI)
16t_c(CI)
16t_c(CI)
2520t_c(CI) ⁽³⁾
32t_c(CI)
10
cycles
ms
cycles
cycles
cycles
cycles
(1) If external oscillator/clock source are used, reset time has to be low at least for 1 ms after V_DD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
(3) The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x DSP Boot ROM Reference Guide (literature number SPRU095) and the TMS320x281x DSP System Control and
Interrupts Reference Guide (literature number SPRU078) for further information.
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications 103
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