TMS320F240_08 Datasheet, PDF (27/105 Pages) Texas Instruments – DSP CONTROLLER

TMS320F240
DSP CONTROLLER
SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002
clock generation (continued)
OSCBYP
XTAL1/CLKIN
XTAL2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ_XOTSACÁÁÁÁÁÁÁ_L ÁÁÁÁÁÁÁ
ÁÁÁÁÁ_MÁÁÁÁÁ_UXÁÁÁÁÁ
Div 2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Div 2}
PLL divide-by-2 bit
(CKCR1.3)
MUX
Phase
Detector
VCO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Feedback
ÁÁÁÁÁÁÁ _Divider
Div 1, 2, 3, 4, 5,
ÁÁÁÁÁÁÁ _{or 9}
ÁÁÁÁÁÁÁ ^PLL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Synchronizing CPUCLK}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Clock Switch}
Clock Mode Bits
(CKCR0.7–6)
PLL multiply ratio
(CKCR1.2–0)
Clock Frequency and PLL Multiply Bits (CKCR1.7–4)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{1-MHz Clock Prescaler}
Prescale Bit (CKCR0.0)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{SYSCLK Prescaler Div 2 or 4}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Watchdog Clock Prescaler}
Figure 8. PLL Clock Module Block Diagram
ACLK
WDCLK
SYSCLK
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