TLFD500PN Datasheet, PDF (27/38 Pages) Texas Instruments – 3.3 V INTEGRATED G.LITE ANALOG FRONT END

DPLL detailed description (continued)
TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999
MCLKIN/
PLLCLKIN
PLL (X4)
NCO_DEF
NCO_DIV_DELAY
CLOCK TO
CONVERTER
+
NCO_DELTA
[3:0]
NCO_DELTA
[7:4]
Figure 7. DPLL Internal Function Block Diagram
Example: Assume MCLKIN/PLLCLKIN=35.328 MHz. When NCO_DEF is programmed as 64, a 2.208 MHz
clock is provided to the ADC converter according to the following formula:
35.328 × 4/64 = 2.208
If NCO_DELTA [7:4] is set to –1, NCO_DELTA [3:0] is set to 3, and NCO_DIV_DELAY is set to 2
(NCO_DIV_DELAY should be the last register to be programmed), register NCO_DEF will change to
63,63,63,64 at the beginning of the third sampling period. Each number (63 or 64) only last one clock
(2.208 MHz) cycle. And the combination 63,63,63,64 occurs only once. Reprogramming of register
NCO_DIV_DELAY is needed if further adjustment is required.
Figure 7 shows the timing of SCLK with the following setting:
NCO_DELTA [7:4] = 1 (Delta)
NCO_DELTA [3:0] = 1 (Repeat)
NCO_DIV_DELAY = 2 (Delay)
Also note that in DPLL mode, the ADC clock will work at 2.208 MHz, 2 times oversampled, (instead of 4.416 MHz
used in the VCXO mode) and the DAC clock will continue to work at 4.416 MHz.
SCLK
16/35.328 MHz
16 SCLKs
21 ns
16/35.328 MHz
16 SCLKs
16/35.328 MHz+1/(4*35.328 MHz)
16 SCLKs
16/35.328 MHz
16 SCLKs
21 ns
ADCLK
NCO_DIV_DELAY is
Programmed by DSP
Start
Counting
1 ADCLK Over
2 ADCLK Over
Figure 8. ADCLK Jitter Example
Jitter is Done
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