THS4532_15 Datasheet, PDF (27/58 Pages) Texas Instruments – THS4532 Ultra Low Power, Rail-to-Rail Output, Fully-Differential Amplifier

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THS4532
SLOS829A – FEBRUARY 2013 – REVISED JULY 2015
Feature Description (continued)
8.3.2 Power Down
The power down pin is internally connected to a CMOS stage which must be driven to a minimum of 2.1 V to
ensure proper high logic.
VS+
ESD Cell
PD
ESD Cell
To
transistor
bases
VS±
Figure 70. Simplified Power-Down Internal Circuit
If 1.8-V logic is used to drive the pin, a shoot through current of up to 100 µA may develop in the digital logic
causing the overall quiescent current to exceed the 2 µA of maximum disabled quiescent current specified in the
Electrical Characteristics: V_S = 2.7 V.
To properly interface to 1.8-V logic with minimal increase in additional current draw, a logic-level translator like
the SN74AVC1T45 device can be used.
Alternatively, the same function can be achieved using a diode and pullup resistor as shown in Figure 71.
3V
1.8V
Controller
VS+
RPU
THS4532
D
PD
Figure 71. THS5432 Power Down Interface to 1.8-V Logic Microcontroller
The voltage at the power down pin will be a function of the supply voltage, input logic level, and diode drop. As
long as the diode is forward biased, the power down voltage is calculated using Equation 3.
V_PD = V_L + V_f
where
• V_L is the logic level voltage.
• V_f is the forward voltage drop across the diode.
(3)
This means for 1.8-V logic, the forward voltage of the diode should be greater than 0.3 V but less than 0.7 V to
keep the power down logic level above 2.1 V and less than 0.7 V respectively.
For example, if 1N914 is selected as the diode with a forward voltage of approximately 0.4 V, the translated logic
voltages will be 0.4 V for disabled operation and 2.2 V for enabled operation.
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