CC2400RSUR Datasheet, PDF (27/84 Pages) Texas Instruments – 2.4 GHz Low-Power RF Transceiver

CC2400
22 Data Buffering
The CC2400 can be used with a buffered or
un-buffered data interface. The data
buffering mode is controlled by the
GRMDM.PIN_MODE[1:0] bits (register
address 0x20).
In un-buffered mode a synchronous data
clock is provided by CC2400 at the DCLK
pin, and the DIO pin is used as data
input/output (see Figure 8).
22.1 Buffered mode
In the buffered mode a 32-byte First-in
First-Out (FIFO) register block is used for
data to be transmitted and data received.
The FIFO is accessed through the
FIFOREG register (address 0x70) using
the SPI interface. Multiple bytes can be
written to the FIFO without repeating the
address if the CSn line is held low.
The crystal oscillator must be running
when accessing the FIFO.
By using the FIFO buffer the data can be
transmitted in bursts. The buffered mode
will therefore offload the host controller
keeping the SPI data rate much lower than
the data rate on the air. This gives also a
great advantage in reducing the current
consumption as the transmitter and
receiver are enabled only in short periods.
It also allows the SPI to operate faster
than the data rate, providing more time for
the MCU to work between data transfers.
More than 32 bytes can be received if the
FIFO is read during reception. In the same
way more than 32 bytes can be
transmitted if new data is written into the
FIFO during transmission. Figure 9 shows
the ways the FIFO can be used during
transmission.
22.2 Buffered mode hardware support
In the buffered mode the FIFO pin can be
used as an interrupt output to assist the
microcontroller in supervising the FIFO.
The FIFO pin can be programmed to give
an interrupt when the FIFO is nearly
empty in TX mode, and nearly full in RX
mode. The threshold (FIFO_THRESHOLD)
is set in INT.FIFO_THRESHOLD[4:0].
In receive mode there will be an interrupt
when the number of received bytes in the
FIFO reaches FIFO_THRESHOLD. The
default value is 30, giving an interrupt
when 30 bytes are received. If the FIFO
becomes full (32 bytes) before it is read,
the reception will be terminated (goes to
the FS_ON state).
In transmit mode there will be an interrupt
when the number of bytes left in the FIFO
reaches 32 - FIFO_THRESHOLD. For the
default value this will happen when there
are 2 bytes left. The transmission is
terminated when the FIFO runs empty
(goes to the FS_ON state). Note that in
order for the FIFO pin to give an interrupt
in transmit mode the number of bytes
must first exceed 32 - FIFO_THRESHOLD.
The FIFO pin activity is illustrated in
Figure 10.
The INT.FIFO_POLARITY bit sets the
polarity of the interrupt signal.
In TX mode, the FIFO pin goes low when
a transmission starts and the preamble is
sent. It will stay low as long as the FIFO is
empty. When data is written to the FIFO, it
will go high. If the number of bytes in the
FIFO goes below the FIFO_THRESHOLD,
the FIFO pin will go low again. If the FIFO
pin goes low, it will stay low until the CRC
has been transmitted.
FIFO_FULL and FIFO_EMPTY signals are
available on the general-purpose I/O pins.
These two signals are affected by
FIFO_THRESHOLD.
In transmit mode, FIFO_EMPTY is low if
the number of bytes in the FIFO is more
than 32-FIFO_THRESHOLD. In receive
mode, FIFO_EMPTY goes low when there
is more than 1 byte in the FIFO.
FIFO_FULL is high if the number of bytes
in the FIFO is greater or equal to
FIFO_THRESHOLD.
SWRS042A
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