BQ24153 Datasheet, PDF (27/40 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support

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bq24153
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SLUSA27 – MARCH 2010
I²C Update Sequence
The IC requires a start condition, a valid I²C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of
a single clock pulse. A valid I²C address selects the IC. The IC performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
For the first update, the IC requires a start condition, a valid I²C address, a register address byte, a data byte.
For all consecutive updates, The IC needs a register address byte, and a data byte. Once a stop condition is
received, the IC releases the I²C bus, and awaits a new start conditions.
S SLAVE ADDRESS
R/W
‘0’ (Write)
A REGISTER ADDRESS A DATA
Data Transferred
(n Bytes + Acknowledge)
A/A ^P
From master to IC
From IC to master
A = Acknowledge (SDA LOW)
A = Not acknowledge (SDA
HIGH)
S = START condition
Sr = Repeated START condition
P = STOP condition
(a) F/S-Mode
F/S-Mode
HS-Mode
F/S-Mode
S HS-MASTER CODE
A ^{Sr SLAVE ADDRESS R/W}
‘0’ (write)
A REGISTER ADDRESS A DATA
Data Transferred
(n Bytes + Acknowledge)
A/A ^P
HS-Mode
Continues
(b) HS- Mode
Figure 34. Data Transfer Format in F/S Mode and H/S Mode
Sr Slave A.
Slave Address Byte
MSB
LSB
X
1
1
0
1
0
1
1
The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB
LSB
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which
contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a
bidirectional I²C-bus interface. Among them, four internal registers have read and write access; and one has only
read access.
Copyright © 2010, Texas Instruments Incorporated
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