TAS5026 Datasheet, PDF (26/48 Pages) Texas Instruments – SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR

One Channel
of TAS5026
TAS5110
Architecture Overview
PWM_AP
PWM_AM
VALID
AP
AM
RESET
BP
BM
OUTA
OUTB
Speaker
Figure 2–12. PWM Outputs and H-Bridge Driven in BTL Configuration
2.5 I²C Serial Control Interface
The TAS5026 has a bidirectional serial control interface that is compatible with the I²C (Inter IC) bus protocol
and supports both 100 KBPS and 400 KBPS data transfer rates for single and multiple byte write and read
operations. This is a slave only device that does not support a multi-master bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5026 supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus
operation (400 kHz maximum). The TAS5026 performs all I²C operations without I²C wait cycles.
The I²C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits
in a system. Data is transferred on the bus serially one bit at a time. The address and data are transferred in
byte (8 bit) format with the most significant bit (MSB) transferred first. In addition, each byte transferred on the
bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and
stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 2–13. The master generates the 7-bit slave address and the read/write (R/W) bit to open
communication with another device and then waits for an acknowledge condition. The TAS5026 holds SDA
low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits
the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte).
All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. I²C An
external pullup resistor must be used for the SDA and SCL signals to set the High level for the bus.
SDA
7 Bit Slave Address R/W A 8 Bit Register Address (N) A ^{8 Bit Register Data For} A ^{8 Bit Register Data For} A
Address (N)
Address (N)
76 5 4 3 210
76 5 4 3 210
76 5 4 3 210
76 5 4 3 210
SCL
Start
Stop
Figure 2–13. Typical I²C Sequence
There are no limits on the number of bytes that can be transmitted between start and stop conditions. When
the last word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is also shown in Figure 2–13.
The 7-bit address for the TAS5026 is 001101X, where X is a programmable address bit. Using the CS0
terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system.
These two addresses are licensed I²C addresses and do not conflict with other licensed I²C audio devices.
To communicate with the TAS5026, the I²C master uses 0011010 if CS0=0 and 0011011 if CS0=1. In addition
to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register
location within the device interface.
SLES041B—November 2002
TAS5026
21