TAS5026 Datasheet, PDF (16/48 Pages) Texas Instruments – SIX CHANNEL DIGITAL AUDIO PWM PROCESSOR

Architecture Overview
Table 2–5. Supported Word Lengths
DATA MODES
WORD
LENGTHS
MOD2
MOD1
Right justified, MSB first
16
0
0
Right justified, MSB first
20
0
0
Right justified, MSB first
24
I2S
16
I2S
20
I2S
24
0
1
0
1
1
0
1
0
Left justified, MSB first
24
1
1
DSP frame
16
1
1
MOD0
0
1
0
1
0
1
0
1
2.1.7.1 I²S Timing
I²S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for
the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
48 or 64 times Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal
changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising
edge of the bit clock. The TAS5026 masks unused trailing data bit positions. Master mode only supports a 64
times Fs bit clock.
2-Channel I2S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
98
54
10
LSB MSB
23 22
98
54
10
LSB
20-Bit Mode
19 18
54
10
19 18
54
10
16-Bit Mode
15 14
10
15 14
10
Figure 2–3. I²S 64-Fs Format
SLES041B—November 2002
TAS5026
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