ADS5484_1 Datasheet, PDF (26/37 Pages) Texas Instruments – 16-Bit, 170/200-MSPS Analog-to-Digital Converters

ADS5484
ADS5485
SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009 ............................................................................................................................................... www.ti.com
Digital Outputs
The ADC provides eight LVDS-compatible, offset binary, DDR data outputs (2 bits per LVDS output driver) and a
data-ready LVDS signal (DRY). It is recommended to use the DRY signal to capture the output data of the
ADS548x (use as a clock output). DRY is source-synchronous to the DATA outputs and operates at the same
frequency, creating a full-rate DDR interface that updates data on both the rising and falling edges of DRY. It is
recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance shortens the
data-valid timing window. The values given for timing (see Figure 1) were obtained with a 5-pF parasitic board
capacitance to ground on each LVDS line. When setting the time relationship between DRY and DATA at the
receiving device, it is generally recommended that setup time be maximized, but this partially depends on the
setup and hold times of the device receiving the digital data. Since DRY and DATA are coincident, it will likely be
necessary to delay either DRY such that DATA setup time is maximized.
The LVDS outputs all require an external 100-Ω load between each output pair in order to meet the expected
LVDS voltage levels. For long trace lengths, it may be necessary to place a 100-Ω load on each digital output as
close to the ADS548x as possible and another 100-Ω differential load at the end of the LVDS transmission line to
terminate the transmission line and avoid signal reflections. The effective load in this case reduces the LVDS
voltage levels by half. The current of all LVDS drivers is set externally with a resistor connected between the
LVDSB (LVDS bias) pin and ground. Normal LVDS current is 3.5 mA per LVDS pair, set with a 10-kΩ external
resistor. For systems with excessive load capacitance on the LVDS lines, reducing the resistor value in order to
increase the LVDS bias current is allowed to create a stronger LVDS drive capability. For systems with short
traces and minimal loading, increasing the resistor in order to decrease the LVDS current is allowable in order to
save power. Table 4 provides a sampling of LVDSB resistor values should deviation from the recommended
LVDS output current of 3.5 mA be considered. It is not recommended to exceed the range listed in the table. If
the LVDS bias current is adjusted, the differential load resistance should also be adjusted to maintain voltage
levels within the specification for the LVDS outputs. The signal integrity of the LVDS lines on the board layout
should be scrutinized to ensure proper LVDS signal integrity exists.
Table 4. Setting the LVDS Current Drive
LVDSB RESISTOR TO GND, Ω
6k
8k
10k (value for normal recommended operation)
12k
14k
16k
18k
20k
LVDS NOMINAL CURRENT, mA
5.6
4.3
3.5
2.8
2.3
2.0
1.7
1.5
26
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5484 ADS5485