ADS5484_1 Datasheet, PDF (25/37 Pages) Texas Instruments – 16-Bit, 170/200-MSPS Analog-to-Digital Converters

ADS5484
ADS5485
www.ti.com ............................................................................................................................................... SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 ´ LOG10 (2 ´ p ´ f_IN ´ j_TOTAL)
(1)
j_TOTAL = (j_ADC² + j_CLOCK²)^1/2
(2)
where:
j_TOTAL = the rms summation of the clock and ADC aperture jitter;
j_ADC = the ADC internal aperture jitter which is located in the data sheet;
j_CLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
f_IN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDCE72010 and CDCM7005. Depending on the jitter requirements, a band pass filter (BPF) is sometimes
required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too
low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed
between the CDC and the BPF, as its harmonics and wide-band noise are reduced by the BPF.
Figure 45 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCE72010
with the clock signal path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult
to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCE72010 output depends largely on the phase
noise of the VCXO/VCO selected, as well as from the CDCE72010 itself.
Board Master
Reference Clock
(High or Low Jitter)
AMP and/or BPF Optional
10 MHz
REF
LVCMOS
AMP
100 MHz
BPF XFMR
CLKP
CLKM
Low Jitter Oscillator
400 MHz
VCO/
VCXO
LVPECL
or
LVCMOS
CDC
(Clock Distribution Chip)
Ex: TI CDCE72010
400 MHz (To Transmit DAC)
100 MHz (To DSP)
100 MHz (To FPGA)
To Other
ADC
TI ADS548x
Consult the CDCE72010 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 45. Optimum Jitter Clock Circuit
B0268-01
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