LM3S8530 Datasheet, PDF (251/526 Pages) Texas Instruments – Stellaris® LM3S8530 Microcontroller

Stellaris® LM3S8530 Microcontroller
11.1 Block Diagram
Figure 11-1. UART Module Block Diagram
System Clock
Interrupt
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTDR
Control/Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
TxFIFO
16 x 8
.
.
.
Baud Rate
Generator
UARTIBRD
UARTFBRD
RxFIFO
16 x 8
.
.
.
Transmitter
(with SIR
Transmit
Encoder)
UnTx
Receiver
(with SIR
Receive
Decoder)
UnRx
11.2
11.2.1
Functional Description
Each Stellaris^® UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 269). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
June 22, 2010
251
Texas Instruments-Production Data