TMS320C6747 Datasheet, PDF (25/203 Pages) Texas Instruments – Floating-point Digital Signal Processor

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TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Table 3-8. External Memory Interface B (EMIFB) Terminal Functions (continued)
SIGNAL NAME
EMB_A[4]/GP7[6]
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
EMB_A[1]/GP7[3]
EMB_A[0]/GP7[2]
EMB_BA[1]/GP7[0]
EMB_BA[0]/GP7[1]
EMB_CLK
EMB_SDCKE
EMB_WE
EMB_RAS
EMB_CAS
EMB_CS[0]
EMB_WE_DQM[3]
EMB_WE_DQM[2]
EMB_WE_DQM[1]/GP5[14]
EMB_WE_DQM[0]/GP5[15]
PIN NO
PTP ZKB
98
D11
100
A10
101
B10
102
C10
103
D10
106
B9
107
C9
86
C14
88
C13
59
K15
110
A8
57
L13
108
D9
-
A12
-
B13
85
C15
60
K14
TYPE ⁽¹⁾
O
O
O
O
O
O
O
O
I/O
O
O
O
O
O
O
O
O
PULL ⁽²⁾
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
MUXED
GPIO
GPIO
DESCRIPTION
EMIFB SDRAM row/column
address.
EMIFB SDRAM band
address.
EMIF SDRAM clock.
EMIFB SDRAM clock enable.
EMIFB write enable
EMIFB SDRAM row address
strobe.
EMIFB column address
strobe.
EMIFB SDRAM chip select 0.
EMIFB write enable/data
mask for EMB_D.
3.6.6 Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions
SIGNAL NAME
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI1_SCS[0]/UART2_TXD/GP5[13]
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
PIN NO
PTP ZKB
SPI0
TYPE ⁽¹⁾
9
N4
I/O
12 R5
I/O
11
T5
I/O
18
P6
I/O
17 R6
I/O
SPI1
8
P4
I/O
7
R4
I/O
16
T6
I/O
PULL ⁽²⁾
MUXED
DESCRIPTION
IPU
UART0, EQEP0B,
GPIO, BOOT
SPI0 chip select.
IPU
UART0, EQEP0A,
GPIO, BOOT
SPI0 enable.
IPD eQEP1, GPIO, BOOT SPI0 clock.
SPI0 data
IPD
slave-in-master-
out.
eQEP0, GPIO, BOOT
SPI0 data
IPD
slave-out-master-
in.
IPU
UART2, GPIO
IPU
SPI1 chip select.
SPI1 enable.
IPD eQEP1, GPIO, BOOT SPI1 clock.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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